Multi-DSP bootstrapping loading system based on serial high-speed interface bus and method thereof

A high-speed interface and loading system technology, which is applied in the field of DSP bootstrapping and loading, can solve problems such as the complexity of DSP loading on multiple sub-boards, and achieve the effects of improving debugging efficiency, simplifying hardware structure, and speeding up loading rate.

Inactive Publication Date: 2013-11-20
CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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Problems solved by technology

[0008] The invention purpose of the present invention is to provide a kind of multi-DSP bootstrap loading system based on the serial high-speed interface bus, to solve the problem of DSP loading complexity on the multi-sub-board in the backplane

Method used

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  • Multi-DSP bootstrapping loading system based on serial high-speed interface bus and method thereof
  • Multi-DSP bootstrapping loading system based on serial high-speed interface bus and method thereof

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Embodiment Construction

[0033] The serial high-speed interface multi-DSP loading technology of the present invention will be further described in detail below in conjunction with a specific implementation case.

[0034] This implementation case is a comprehensive backplane system, such as figure 1 As shown, the backplane system includes an IO interface sub-board to coordinate and process all the interface functions and transmission relay functions of the backplane system. It also includes 4 digital signal processing sub-boards, and each signal processing sub-board uses a TI The company supports the DSP chip TMS320C6455 of serial high-speed interface.

[0035] On the IO interface daughter board of the backplane, there is Xilinx FPGA chip Virtex-5 and its peripheral loading circuit (including external non-volatile memory-Flash and JTAG interface circuit), and the RapidIO switch chip (RapidIO Switch Core) uses a IDT's CPS1848.

[0036] FPGA and DSP form a master-slave relationship through a serial hig...

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Abstract

The invention discloses a multi-DSP bootstrapping loading system based on a serial high-speed interface bus and a method thereof. The serial high-speed interface bus is adopted in a backing plate system to carry out interconnection and communication between chips, DSPs support the serial high-speed interface technology, an FPGA chip supporting a serial high-speed interface is selected, is not directly connected with DSP chips and is communicated with the DSP chips through a switching module, and the communication mode is that an information packet is sent to the switching module through an FPGA and the switching module looks up a chip interface corresponding to a chip of an information packet header according to the ID of the chip of the information packet header to carry out packet transmission. The multi-DSP bootstrapping loading system not only simplifies the hardware structure and improves debugging efficiency, but also quickens the loading rate of the DSPs.

Description

technical field [0001] The invention designs a DSP bootstrap loading method based on a serial high-speed interface boot mode, and particularly relates to a system and a method for simultaneously bootstrapping multiple DSPs through a serial high-speed interface bus network. Background technique [0002] Digital signal processing technology is widely used in radar, communication, image processing and other fields, many of which have a large amount of processing calculations and complex algorithm structures, and require high-speed real-time, high-performance, and flexible completion of various processing tasks. DSP has been widely used in digital signal processing technology because of its high computing precision and strong real-time performance. [0003] In the DSP (Digital Signal Processing) system, the application program must be loaded to make it an independent offline operating system. In order to realize the loading of the application program, the DSP must be guided and...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/445
Inventor 羿昌宇祖翔宇李裕许生
Owner CHINESE AERONAUTICAL RADIO ELECTRONICS RES INST
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