Simulation method of LDMOS (laterally diffused metal oxide semiconductor) array

Abstract

The invention discloses a simulation method of an LDMOS (laterally diffused metal oxide semiconductor) array. The simulation method includes that a macro-model is established aiming at an LDMOS layout array structure according to sizes Wy variable in width and N arched doors in a layout, the macro-model is internally embedded with a computational formula of a total equivalent width of a drain terminal drift region of an LDMOS as well as an LDMOS subcircuit model with an equivalent channel width being the total equivalent width of a drain terminal drift region of the LDMOS, the total equivalent width of the drain terminal drift region of the LDMOS array can be automatically calculated by a user inputting partially adjustable variables in the layout, electrical characteristics results, corresponding to the LDMOS array, of simulation can be outputted, and meanwhile, corrected parameters are added into the model. Flexibility and precision of the model are improved by means of fitting, great convenience is brought for designers to simulate current of the LDMOS array different in size, and design efficiency is improved accordingly.

Description

technical field [0001] The invention relates to a semiconductor simulation test technology, in particular to a simulation method of an LDMOS array. Background technique [0002] LDMOS (Lateral Diffused Medal 0xide Semiconductor, laterally diffused metal oxide semiconductor) is widely used in power circuit design in analog circuits. LDMOS can withstand high voltage and can provide very large drive current through array arrangement. When designing circuits , after skillfully arranging LDMOS on the layout, a special array structure will be obtained, and the designer will call this array structure as an independent cell library. [0003] The structure of a common LDMOS array is as follows figure 1 , figure 2 As shown, this kind of LDMOS array is composed of many individual LDMOSs connected in parallel, and this kind of LDMOS array includes a drain drift region 15, a drain metal layer 14, N arched gates 13, and N+1 rows of vertical drain contact holes 11 , N+2 rows of longitu...

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Problems solved by technology

[0011] The structure of this kind of LDMOS array is affected by the arched gate 13 and the drain terminal metal layer 14. The shape of the drain drift region 15 of the LDMOS above the arched gate 13 of the layout is relatively special, and the current flows from the drain terminal to the source terminal. The distribution is uneven, so it is difficult to calculate the equivalent width of the drain drift region of this type of LDMOS array in this area

Moreover, the number N of arched gates is different, and the total equivalent width of the drain drift region of this kind of LDMOS array is also different.

[0012] Since the total equivalent width of the drain drift region of this type of LDMOS array cannot be accurately calculated, it is difficult to simulate for this type of LDMOS array

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