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Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof

A system-level chip, first sealing and then etching technology, applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc.

Active Publication Date: 2014-01-15
江阴芯智联电子科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to overcome the above-mentioned shortcomings, and provide a three-dimensional system-in-package structure and process method for sealing first and then etching chips, which can solve the problem that traditional metal lead frames or multilayer circuit substrates cannot embed chips and passive components. The problem of packaging function integration and the problem of traditional organic substrates requiring thinner line width and narrower line-to-line spacing

Method used

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  • Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof
  • Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof
  • Firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and technology method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0227] Example 1: single-layer circuit single-chip front-mounted single-turn pins (1)

[0228] see Figure 23, the present invention is a three-dimensional system-on-chip front-mounted bump package structure that is sealed first and etched later. It includes a base island 1 and pins 2. Conductive pillars 3 are arranged on the front side of the pins 2. The front side of the base island 1 is conductive or The non-conductive adhesive substance 6 is equipped with the first chip 4, and the front of the first chip 4 is connected with the front of the pin 2 through the first metal wire 5, and the area of ​​the front of the base island 1 and the pin 2 is conductive. The pillar 3, the first chip 4 and the peripheral area of ​​the first metal wire 5 are all encapsulated with a first molding compound or epoxy resin 9, and the first molding compound or epoxy resin 9 is flush with the top of the conductive pillar 3, so The surface of the conductive pillar 3 exposed to the first molding co...

Embodiment 2

[0276] Embodiment 2: single-layer circuit single-chip front-mounted single-turn pins (2)

[0277] see Figure 51 , the present invention is a three-dimensional system-on-chip front-mounted bump package structure that is sealed first and etched later. It includes a base island 1 and pins 2. Conductive pillars 3 are arranged on the front side of the pins 2. The front side of the base island 1 is conductive or The non-conductive adhesive substance 6 is equipped with the first chip 4, the front of the first chip 4 is connected to the front of the pin 2 through the first metal wire 5, the base island 1 and the front area of ​​the pin 2 and the conductive pillar 3. The peripheral areas of the first chip 4 and the first metal wire 5 are encapsulated with a first molding compound or epoxy resin 9, and the first molding compound or epoxy resin 9 is flush with the top of the conductive pillar 3, and the first molding compound or epoxy resin 9 is flush with the top of the conductive pill...

Embodiment 3

[0332] Embodiment 3: Multi-layer circuit single-chip front-mounted single-turn pins

[0333] see Figure 99 , the present invention is a three-dimensional system-on-chip front-mounted bump package structure that is sealed first and etched later. It includes a base island 1 and pins 2. Conductive pillars 3 are arranged on the front side of the pins 2. The front side of the base island 1 is conductive or The non-conductive adhesive substance 6 is equipped with the first chip 4, and the front of the first chip 4 is connected with the front of the pin 2 through the first metal wire 5, and the area of ​​the front of the base island 1 and the pin 2 is conductive. The pillar 3, the first chip 4 and the peripheral area of ​​the first metal wire 5 are all encapsulated with a first molding compound or epoxy resin 9, and the first molding compound or epoxy resin 9 is flush with the top of the conductive pillar 3, so The surface of the conductive pillar 3 exposed to the first molding com...

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Abstract

The invention relates to a firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure and a technology method of the firstly-packaged secondly-etched three-dimensional system level chip front-installed bump packaged structure. The packaged structure comprises a base island (1) and pins (2). Electric conduction pillars (3) are arranged on the front faces of the pins (2), a first chip (4) is front installed on the front face of the base island (1), the peripheral areas of the electric conduction pillars (3), the first chip (4) and a first metal wire (5) are all packaged with first molding compounds or epoxy resin (9), and a second chip (7) is front installed on the back face of the base island (1). The back areas of the base island (1) and the pins (2) and the peripheral areas of the second chip (7) and a metal wire (8) are all packaged with second molding compounds or epoxy resin (10). First metallic balls (17) are arranged on the electric conduction pillars (3). The packaged structure has the advantages that the problems that due to the fact that a traditional metallic lead frame or a traditional organic substrate can not be buried into an object, the integration level of the whole packaging function is limited, and the traditional organic substrate needs a smaller line width and a narrower distance between lines are solved.

Description

technical field [0001] The invention relates to a three-dimensional system-level chip front-mount bump packaging structure and a process method after sealing first and etching later, and belongs to the technical field of semiconductor packaging. Background technique [0002] Traditional four-sided leadless metal lead frame package structure such as Figure 104 As shown, the main manufacturing process is to take metal sheets for chemical etching and metal plating to make a base island for carrying chips and a metal lead frame with inner and outer pins, and then perform one-sided chip loading and wire bonding on this basis. , encapsulation and other packaging processes. [0003] The traditional organic multilayer circuit substrate packaging structure such as Figure 105 As shown, the main process is to form a multi-layer circuit board by stacking the core material of the glass fiber board by accumulating materials, opening holes between the circuit layers by laser drilling, a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/48H01L21/56H01L23/495H01L23/31
CPCH01L24/97H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73265H01L2224/92247H01L2224/97H01L2924/15311H01L2924/181H01L2924/00014H01L2924/00H01L21/4821H01L21/4882H01L21/561H01L23/3114H01L23/49534H01L23/49548H01L23/49568
Inventor 梁志忠梁新夫林煜斌张凯章春燕
Owner 江阴芯智联电子科技有限公司
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