NAND gate circuit, displayer backboard and displayer

Abstract

The invention provides an NAND gate circuit, a displayer backboard and a displayer. The NAND gate circuit comprises at least two input transistors, at least two upward-pulling modules and at least two input control transistors. A first electrode of each input transistor is connected with the output end of a second electrical level through one corresponding upward-pulling module. Each input control transistor is used for controlling the electric potential the control end of the corresponding upward-pulling module connected with the first electrode of the input transistor to be a first electrical level when an input signal received by a grid electrode of the input control transistor is the second electrical level. The two upward-pulling modules are used for disconnecting the output end of the second electrical level and the output end of the NAND gate circuit when all the input signals are the second electrical level and used for connecting the output end of the second electrical level and the output end of the NAND gate circuit when not all the input signals are the second electrical level. According to the NAND gate circuit, when a depletion mode TFT is adopted, lossless transmission of output of an NAND gate can be achieved, and rail-to-rail output of the NAND is achieved.

Description

technical field [0001] The invention relates to the field of display technology, in particular to a NAND gate circuit, a display backplane and a display. Background technique [0002] At present, there are many kinds of processes for manufacturing the backplane of display devices, such as a-Si (amorphous silicon) TFT transistor (Thin Film Transistor, thin film field effect transistor) display device, LTPS (Low Temperature Poly-silicon, low temperature polysilicon) TFT display device , Oxide TFT transistors (oxide TFT transistors) display devices, etc., a-Si TFT transistors have the disadvantages of low mobility and poor stability, and LTPS TFT transistors are not suitable for the preparation of large-scale panels. The I-V transfer characteristic of the oxide TFT transistor is usually a depletion type, that is, when the gate-source voltage Vgs of the oxide TFT transistor is zero, the oxide TFT transistor is still turned on. [0003] The depletion mode TFT transistor brings g...

AI Technical Summary

Problems solved by technology

exist figure 2 Among them, T1, T2, and T3 are respectively the first N-type transistor, the second N-type transistor, and the third N-type transistor, IN1 and IN2 respectively mark the first input signal and the second input signal, and OUT marks the output signal. VDD indicates high level, VSS indicates low level; T3 forms a diode connection, which acts as a pull-up resistor. When IN1 and IN2 are high at the same time, T1 and T2 are turned on at the same time, and OUT is pulled down; but because T3 is Long pass, there is a DC path from VDD to VSS, and the output low level is determined by the voltage division of the series resistance of T3 and T1, T2, and cannot reach VSS; when one of IN1 and IN2 is low or both are low, T1 and IN2 T2 is cut off. Since T3 is connected by a diode, OUT is equal to VDD-VTH, and VTH is the threshold voltage of T3. At this time, OUT cannot reach VDD.

It can be seen from the above that the traditional NMOS (N-Mental-Oxide-Semiconductor, n-type metal-oxide-semiconductor) structure of the NAND gate has the disadvantages that the output cannot be rail-to-rail and the leakage current is large.

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