Design method for semiconductor integrated circuit device

Abstract

The invention provides a design method for a semiconductor integrated circuit (IC) device and belongs to the technical field of semiconductor integrated circuit design. The method comprises the steps of defining performance factors for reflecting integrated circuit design specifications at a circuit level; performing the mapping of the performance factors to device parameters of a device level; and optimizing design variables of the device according to integrated circuit design performance parameters so that the maximum values of the performance factors can be taken. An integrated circuit at least comprises the device. According to the method, the design specifications at the circuit level are considered into the analysis modeling process of the device used by the circuit, the circuit performances can be improved on the whole, for example, power consumption of a static random access memory (SRAM) is reduced, the reading time is shortened, and the reliability is improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit (Integrated Circuit, IC) design, and relates to a semiconductor integrated circuit device optimization design method with circuit performance as the focus (circuit aware). Background technique [0002] As integrated circuit technology continues to develop according to Moore's law, the devices used in it continue to scale down, so it is becoming more and more difficult to obtain ideal device performance. [0003] Taking MOS tube devices as an example, in the 130nm line width technology generation, sub-threshold leakage current is the only main leakage current in CMOS tube devices. However, with the scaling down of MOS tube devices, as To maintain sufficient gate coupling to the device channel and reduce the short channel effect, the thickness of the gate oxide layer is also continuously scaled down, which directly leads to a significant increase in the direct tunneling leak...

AI Technical Summary

Problems solved by technology

However, when entering the nano-scale technology generation, for example, the feature size is below 90nm, as mentioned above, the various leakage currents in the MOS tube device are more, and it becomes more and more serious with the reduction of the feature size. figure 2 When using the design method shown, it is difficult for its IC to achieve low leakage in overall performance while maintaining high performance

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