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TSV (through silicon via) through hole insulation layer test structure based on SOI (silicon on insulator) substrate

A substrate and test point technology, applied in the field of microelectronics, can solve the problems of increasing the reliability of SOI three-dimensional integrated devices, withstand voltage and leakage tests, effective insulating layers, etc., to avoid economic losses, improve reliability, and reduce costs. Effect

Active Publication Date: 2014-03-12
珠海天成先进半导体科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] In order to overcome the deficiency that the existing technology cannot perform complete and effective insulating layer withstand voltage and leakage tests on SOI-based TSV via holes, the present invention provides a TSV via-hole insulating layer test structure based on SOI substrates, which can separately test the top layer The two parts of the TSV through-hole insulating layer, silicon and underlying silicon, are subjected to withstand voltage and leakage tests, which can not only realize a complete TSV through-hole insulating layer test, evaluate the quality of the TSV through-hole insulating layer as a whole, but also effectively judge the top and bottom parts TSV through-hole insulating layer defect exists area, which is convenient to screen out the wafer with TSV through-hole defect, and increases the reliability of SOI three-dimensional integrated device

Method used

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  • TSV (through silicon via) through hole insulation layer test structure based on SOI (silicon on insulator) substrate
  • TSV (through silicon via) through hole insulation layer test structure based on SOI (silicon on insulator) substrate
  • TSV (through silicon via) through hole insulation layer test structure based on SOI (silicon on insulator) substrate

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Embodiment 1

[0014] like image 3 As shown, the SOI wafer substrate is P-type silicon, and the thickness of the buried oxide layer 13 is Top Silicon 12 Thickness The bottom silicon 14 has a thickness of 80 μm, the TSV copper pillar 5 has a diameter of 30 μm, the TSV through-hole insulation layer 2 has a thickness of 0.6 μm, the barrier layer TaN and copper seed 3 have a thickness of 0.4 μm, and the bottom insulation layer 4 of the silicon substrate has a thickness of 1 μm. The No. 2 ohmic contact test point 16 is located on the back side of the underlying silicon 14, wherein the active region 7 of the No. 2 ohmic contact test point 16 is a heavily doped P+ region, and the implantation depth The aluminum metal pad 8 is a square of 5 μm × 5 μm; the first ohmic contact test point 15 is located on the front side of the top layer silicon 12, and the pad 8 is 30 μm away from the center of the TSV through hole, and the first ohmic contact test point 15 has an active area 7 For the heavily do...

Embodiment 2

[0017] like image 3 As shown, the SOI wafer substrate is N-type silicon, and the thickness of the buried oxide layer 13 is Top Silicon 12 Thickness The bottom silicon 14 has a thickness of 80 μm, the TSV copper pillar 5 has a diameter of 25 μm, the TSV through-hole insulation layer 2 has a thickness of 0.4 μm, the barrier layer TaN and copper seed 3 have a thickness of 0.2 μm, and the bottom insulation layer 4 of the silicon substrate has a thickness of 1 μm. The No. 2 ohmic contact test point 16 is located on the back side of the underlying silicon 14, wherein the active region 7 of the No. 2 ohmic contact test point 16 is a heavily doped N-region, and the implantation depth The aluminum metal pad 8 is a square of 8 μm×8 μm; the first ohmic contact test point 15 is located on the front side of the top layer silicon 12, and the pad 8 is 25 μm away from the center of the TSV through hole, and the first ohmic contact test point 15 has an active area 7 For the heavily doped...

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Abstract

The invention provides a TSV (through silicon via) through hole insulation layer test structure based on an SOI (silicon on insulator) substrate. No. 1 and No. 2 ohm contact test points are respectively manufactured at the front side of top layer silicon and the back side of bottom layer silicon, each ohm contact test point comprises a heavy doping active region and an aluminum metal press welding point, during the testing, a No. 1 direct current variable voltage source is connected with a No. 1 ampere-voltage meter in series and is then connected with a TSV copper post and the aluminum metal press welding point of the No. 1 ohm contact test point in series through a metal probe, and the No. 2 direct current variable voltage source is connected with a No. 2 ampere-voltage meter in series and is then connected with the TSV copper post and the aluminum metal press welding point of the No. 2 ohm contact test point in series through a metal probe. The TSV through hole insulation layer test structure has the advantages that the complete TSV through hole insulation layer test can be realized, the TSV through hole insulation layer quality is integrally evaluated, the existing regions of defects of the two-part (top and bottom) TSV through hole insulation layers can be effectively judged, the wafers, with the defects, of the TSV through holes can be conveniently screened and removed, and the reliability of an SOI three-dimensional integrated device can be improved.

Description

technical field [0001] The invention relates to the technical field of microelectronics. Background technique [0002] The quality of the insulating layer of the TSV through hole has a great impact on the quality of the three-dimensional integration process and the reliability of the device. By designing the test structure of the TSV insulating layer and performing withstand voltage and leakage tests, the quality of the TSV insulating layer can be evaluated to ensure the quality of the three-dimensional integration process. and device reliability. At present, the most commonly used TSV via hole insulation layer test structure is based on the structure proposed in the document "Electrical and Morphological Assessment of Via Middle and Backside Process Technology for 3D Integration (ECTC201262nd)". This structure (see figure 1 ) need to make ohmic contacts on the back of the wafer (including the active area and aluminum metal contact points), and then connect the front of the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/12G01R31/02H01L23/544
Inventor 单光宝刘松孙有民李翔贺欣
Owner 珠海天成先进半导体科技有限公司
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