47results about How to "Test complete" patented technology

The invention discloses a method for diagnosing a fault of a transformer on the basis of a clustering algorithm and a neural network. The method comprises the following steps that (a) the type of the fault is determined according to an IEC standard and a DL/T722-2000 guideline, and the characteristic quantities of a fault sample set are selected from an original sample set; (b) clustering is carried out on samples by utilizing a K-means clustering method; (c) an RBF neural network is established; (d) parameter learning is carried out to determine the number, the center position, the width and the output weight of hidden layers; (e) optimization training is carried out by adopting PSO to determine the positions of the centers of the hidden layers, and the number, the width and the weight of the hidden layers are determined by utilizing a test method, a minimum distance method and a pseudo-inverse method respectively; (f) training samples are input, the posterior probability is solved, and the type of the fault is judged. According to the method for diagnosing the fault of the transformer on the basis of the clustering algorithm and the neural network, the training samples and the test samples can be evenly divided from the total samples, more complete test on the neural network can be carried out by good test samples, and therefore the neural network can be evaluated correctly and reasonably.

The present invention discloses a method to send the simulating AT order. The present invention opens the serial port and builds the AT order communication passage with the mobile terminal(UE) through starting the PC side application procedure; the present invention chooses the response result of the AT order which needs to be enforced in the simulating software, writes the chosen response result in the deploy document through the simulating software, then makes the PC side application procedure send AT order to the UE and wait for the UE sending order result, after the PC side application procedure reads the AT order result and the AT order response result in the deploy document, the present invention replaces the order result sent by the UE according to the necessity; if the result is sent by the simulating software initiatively, the present invention puts the AT order response result in the document in the back of the communication terminal sending order result and sends the last result to the upper to handle; the upper takes the result as the communication terminal sending result when the upper handles the result input by the simulating software to realize the needing result.

The invention belongs to the technical field of bridge safety detection, and discloses a bridge influence surface identification method considering vehicle wheel load spatial distribution, which comprises the following steps: 1) loading a bridge with a calibration vehicle by adopting a specific loading path, and collecting response data; 2) numbering the two-dimensional positions of the bridge andestablishing a mathematical model of influence surface identification; and 3) solving the influence surface identification equation by adopting an L2 regularization method. According to the method, actual measurement information of a loading vehicle passing through a bridge of a specific path and bridge response caused by the loading vehicle is utilized, solving is carried out through a bridge two-dimensional position number and a mathematical model established on the basis of the bridge two-dimensional position number, and the influence line recognition precision can be greatly improved; meanwhile, the boundary which cannot be recognized by a traditional method can be effectively reconstructed, and the method has good engineering practical value.

An automatic test system for testing integrated circuits (ICs) and overall system is composed of a rack, at least one computer for test purpose and arranged in said rack for carrying and testing an IC, at least one automatic connect/disconnect mechanism for plugging the IC to be tested in the testing computer or self-test computer and disconnecting it, and at least one controller for controlling the connection and disconnection of IC and its test process. After the ICs to be tested are plugged in the testing computer, it becomes a complete computer for running application and test programs and performing the test of overall system.

The invention discloses a presetting bit precision automatic testing system and a testing method thereof. The presetting bit precision automatic testing system comprises a testing system unit, tested equipment and template placing location unit. The testing method comprises the steps of: placing a calibration template, and adjusting zooming times of a camera so that the calibration template occupies an appropriate field-of-view scope of a lens; inputting a distance into a control module for setting; clicking calibration to run the calibration template, so as to obtain a transformation model of image pixels and spatial positions; setting a presetting bit for acquiring an image; recalling the presetting bit for acquiring an image; matching the images of the presetting bit and calculating a pixel deviation; calculating a rotation angle deviation of the tested equipment; testing presetting bit deviations of a uniform presetting bit under different control; and testing presetting bit deviations at different positions. Compared with the prior art, the presetting bit precision automatic testing system based on image processing disclosed by the invention is simple and rapid in system installation, has automatic testing operation, is more complete in tests, and achieves high test precision in the actual application.

The invention discloses a display panel and a testing method thereof. The display panel comprises a first lead circuit and a second lead circuit, the second lead circuit is electrically connected with one in a circuit to be tested and the first lead circuit, and the second lead circuit and the other one of the circuit to be tested and the first lead circuit are arranged in an insulating manner at intervals. The testing method includes the steps: electrically connecting the second lead circuit with the other one of the circuit to be tested and the first lead circuit, and enabling the first lead circuit to be electrically connected with the circuit to be tested; testing the circuit to be tested or a circuit device connected with the circuit to be tested by the first lead circuit; disconnecting the second lead circuit and further disconnecting electrical connection between the circuit to be tested and the first lead circuit after testing is finished. By the aid of the mode, all signal wires in the display panel can be accurately and completely tested, and real and effective data are provided for design verification of the display panel.

The invention discloses a memory test system and a memory test method which are applied to a computer which comprises a memory and an operation system. The method comprises the following steps: setting a jumper cap on the main board of the computer through GPIO and powering up the computer to carry out system initialization; detecting whether the level of the GPIO on the main board is low level; when the level of the GPIO is high level, mapping the virtual address used by the operation system on the first physical address of the memory; when the level of the GPIO is low level, mapping then virtual address used by the operation system on the second physical address of the memory; executing the memory test program to test the memory part which is not mapped; detecting whether the memory is completely tested; when the memory is not completely tested, changing the level of the GPIO through the changing of the jumper cap setting on the GPIO. Through the memory test system and method, the virtual address used by the operation system can be mapped to different physical memory addresses so as to integrally test the whole physical memory of the computer.

The invention discloses a method for testing main insulation and turn-to-turn insulation of a low-voltage scattered-wound variable frequency motor, and the method comprises the steps: S1, inputting 0-220V AC voltage, and carrying out the voltage regulation of the AC voltage; s2, boosting the voltage signal after voltage regulation; s3, transmitting the boosted voltage signal through a common high-voltage bus, and switching a test branch by changing the state of a switching relay; s4, when the turn-to-turn insulation is tested, increasing the voltage, by using the generated high-frequency pulse signal, of the variable frequency motor winding, and testing the turn-to-turn insulation by means ofthe pulse signal; when the main insulation is tested, boosting, by using the sine voltage signal transmitted by the common high-voltage bus, the variable frequency motor winding, and grounding the motor shell, and testing, by using the sine signal, the main insulation. The invention further provides a topological structure for testing the main insulation and the turn-to-turn insulation of the low-voltage scattered-wound variable frequency motor. According to the invention, by sharing the high-voltage bus, the main insulation and the turn-to-turn insulation can be jointly tested in the same test system, the experiment steps and the experiment equipment are reduced, and the experiment efficiency is greatly improved.

The invention discloses a test method and device for an embedded program in a rail transit vehicle. The method comprises the steps: S1, carrying out the program instrumentation of a tested program, enabling the tested program to cover each code block in the tested program, carrying out the compiling and conversion of the program after instrumentation, and generating a target operation program; S2,running the target running program, collecting information sent by each probe of instrumentation in the running process of the target running program, and sending the information; S3, receiving the information sent by each probe, and obtaining the coverage state of completing the test in the tested program according to the received information; the device comprises a running program generation module, a probe information collection module and a test state collection module. The method is simple in test implementation, low in test cost, capable of achieving embedded program gray box test and obtaining the test coverage state at the same time, sufficient in test and good in effect.

The invention is applicable to the technical field of computers, and provides a file sequence processing method and device, terminal equipment and a storage medium. The method includes obtaining a to-be-processed source file; determining each action node label contained in the to-be-processed source file and the sequence of each action node label to obtain action execution sequence information, wherein the action node label is a node label used for describing a test action; according to the action execution sequence information, calling an execution function corresponding to each action node label from a preset dynamic link library in sequence, and executing a test sequence described by the source file, wherein the execution function is a computer function which is correspondingly createdfor various action node tags in advance and is used for realizing test actions described by the action node tags; the preset dynamic link library is a dynamic link library obtained by compiling program files containing the execution functions in advance. According to the embodiment of the invention, the formally described test sequence in the source file can be actually operated.

The invention discloses a test system and method used for an inverter power supply capable of parallel operation. The test system comprises a power source to be tested with an input end and an output end, a power supplying source supplying power to the power source to be tested, a test driving and controlling device, an input control device and an output control device, wherein the test driving and controlling device is connected with the input end and the output end, the input control device is connected with input end and the test driving and controlling device, and the output control device is connected with the output end and the test driving and controlling device. According to the test system and method, the testing procedures are simple, the testing accuracy is high and the testing efficiency can be effectively improved.

The invention relates to a fire-extinguishing bottle simulation device and method, belongs to the technical field of fire extinguishing and explosion suppression, and solves the problems that an existing fire extinguishing bottle simulator is low in simulation degree and cannot truly reflect the explosion starting process of an electric explosion tube of a fire extinguishing bottle, and a pressureswitch and a pipeline pressure switch of the fire extinguishing bottle are disconnected. The fire-extinguishing bottle simulation device comprises: an electric detonator driving signal acquisition circuit which is used for simulating a circuit for starting an electric detonator of a fire extinguishing bottle according to the starting time of the electric detonator when the fire extinguishing suppression system gives out a fire alarm; a fire extinguishing bottle pressure switch circuit which is used for simulating a circuit for switching off a fire extinguishing bottle pressure switch at a first preset time after the electric detonator is started, wherein the first preset time is the bottle spraying time of the fire extinguishing bottle; and a pipeline pressure switch circuit which is usedfor simulating the disconnection of the pipeline pressure switch at a second preset time after the disconnection of the fire extinguishing bottle pressure switch, wherein the second preset time is the injection time of residues in the pipeline of the fire extinguishing bottle. The simulation degree of the fire extinguishing bottle simulation device is improved.