Fin type field effect transistor and forming method thereof

Abstract

The invention relates to a fin type field effect transistor and a forming method thereof. The fin type field effect transistor comprises a semiconductor substrate, a fin part, first dielectric layers, a gate structure, a source region, a drain region and contact metal layers, wherein the fin part is positioned on the surface of the semiconductor substrate; the first dielectric layers are positioned on two sides of the fin part, and the surfaces of the first dielectric layers are lower than the top of the fin part; the gate structure is positioned on the fin part and covers parts of the top and the side wall of the fin part; the source region and the drain region are positioned on two sides of the gate structure; the contact metal layers are positioned on the surfaces of the source region and the drain region and have stretching stress. The carrier mobility of the fin type field effect transistor is high.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a fin field effect transistor and a forming method thereof. Background technique [0002] MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. However, when the semiconductor technology enters the node below 30 nanometers, the control ability of the traditional planar MOS transistor to the channel current becomes weak, causing serious leakage current. A Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a semiconductor fin with a high aspect ratio, a gate structure covering part of the top and sidewalls of the fin, and in the Channel regions and source / drain regions of transistors are formed in the fins. [0003] figure 1 A schematic diagram of a three-dimensional structure of a fin field effect transistor in the prior art is shown. Such as figur...

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Problems solved by technology

However, with the development of semiconductor technology, such as the nitride cap layer (Nitride-Cap) stress layer, due to the high dielectric constant will increase the parasitic capacitance in the device, it is no longer suitable for highly integrated fin field effect transistor technology

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