Method of causing partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability

A chip system and reliability technology, applied in the direction of program control device, program loading/starting, etc., can solve the problems of complex design and difficult implementation, and achieve the effects of improving reliability, overcoming large resource consumption, and overcoming complex design

Inactive Publication Date: 2014-04-02
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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Problems solved by technology

The error correction circuit monitors the key signals of each module in real time and corrects the detected error signals in time. It has a good fault tolerance effect, but it also has the disadvantages of complex de

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  • Method of causing partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability
  • Method of causing partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability
  • Method of causing partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability

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Embodiment Construction

[0033] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0034] The present invention proposes a highly reliable implementation method based on a partially configurable FPGA chip system, which performs repeated partial configuration on the FPGA chip without affecting the normal operation of the chip, to eliminate accumulated logic errors, and has the characteristics of low resource consumption .

[0035] like figure 1 as shown, figure 1 It is a flow chart of a method for making a partially configurable FPGA chip system with high reliability provided by the present invention. The FPGA chip supports partial configuration, and the method includes the following steps:

[0036] Step 101: read the design input file; the design input file includes a design file described by Verilog ...

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Abstract

The invention discloses a method of causing a partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability. The method comprises the following steps of reading a design input file; synthesizing the design input file; scheduling and distributing idletime of each function module in the FPGA chip by utilizing a scheduling algorithm and combining redundancy so as to cause each function module in the FPGA chip to have enough idle time; mapping a logic unit to a logic block; carrying out layout wiring on the mapped design; generating a code stream file according to a result containing scheduling information after layout wiring; downloading the generated code stream file to the FPGA chip; automatically and continuously reconfiguring the different function modules while the FPGA chip works normally. The method solves the problem that the system cannot work normally due to a position overturn mistake of an FPGA logic module can be solved, the vice of larger consumption of triple-modular redundant resources is overcome, and the reliability of the chip is improved without influencing the normal work of the chip.

Description

technical field [0001] The invention relates to the field of field programmable gate array (FPGA) and electronic design automation technology, in particular to a method for enabling a partially configurable FPGA chip system to have high reliability under the influence of space radiation effects. Background technique [0002] FPGA is Field Programmable Logic Gate Array, which has the advantages of short development cycle, low cost, and strong flexibility, and has been widely used in the aerospace field. However, there are a large number of high-energy particles such as radiating electrons and high-energy protons in space. When these particles hit the chip, they will produce single-event flipping, total dose effect, single-event locking and other effects, which pose a serious threat to the reliability of FPGA chips. [0003] With the development of FPGA process technology, the integration level is getting higher and higher. Considering the impact of power, low voltage is intro...

Claims

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Application Information

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IPC IPC(8): G06F9/445
Inventor 刘贵宅于芳郭旭峰李艳
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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