Method of causing partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability

Abstract

The invention discloses a method of causing a partially-configurable FPGA (Field Programmable Gate Array) chip system to have high reliability. The method comprises the following steps of reading a design input file; synthesizing the design input file; scheduling and distributing idletime of each function module in the FPGA chip by utilizing a scheduling algorithm and combining redundancy so as to cause each function module in the FPGA chip to have enough idle time; mapping a logic unit to a logic block; carrying out layout wiring on the mapped design; generating a code stream file according to a result containing scheduling information after layout wiring; downloading the generated code stream file to the FPGA chip; automatically and continuously reconfiguring the different function modules while the FPGA chip works normally. The method solves the problem that the system cannot work normally due to a position overturn mistake of an FPGA logic module can be solved, the vice of larger consumption of triple-modular redundant resources is overcome, and the reliability of the chip is improved without influencing the normal work of the chip.

Description

technical field [0001] The invention relates to the field of field programmable gate array (FPGA) and electronic design automation technology, in particular to a method for enabling a partially configurable FPGA chip system to have high reliability under the influence of space radiation effects. Background technique [0002] FPGA is Field Programmable Logic Gate Array, which has the advantages of short development cycle, low cost, and strong flexibility, and has been widely used in the aerospace field. However, there are a large number of high-energy particles such as radiating electrons and high-energy protons in space. When these particles hit the chip, they will produce single-event flipping, total dose effect, single-event locking and other effects, which pose a serious threat to the reliability of FPGA chips. [0003] With the development of FPGA process technology, the integration level is getting higher and higher. Considering the impact of power, low voltage is intro...

AI Technical Summary

Problems solved by technology

The error correction circuit monitors the key signals of each module in real time and corrects the detected error signals in time. It has a good fault tolerance effect, but it also has the disadvantages of complex design and difficult implementation.

Periodic reconfiguration of the FPGA can clear accumulated errors, which has the advantage of being simple to implement, but it cannot be done while the FPGA chip is working properly

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