Packaging structure

A technology of packaging structure and plastic sealing layer, which is applied in the direction of electrical components, electric solid devices, circuits, etc., can solve the problems of low packaging efficiency, achieve the effects of improving efficiency, preventing short circuit, and reducing area

Active Publication Date: 2014-04-16
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Existing lead frame packages can only be packaged for a single semiconductor chip and lead frame, and the packaging efficiency is low

Method used

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Experimental program
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Embodiment Construction

[0024] When encapsulating existing leadframes, please refer to the figure 1 First, the wafer needs to be cut to form semiconductor chips 14 one by one, and then metal wires 17 are formed through a wire bonding process. The metal wires 17 connect the pads 15 on the semiconductor chips 14 with the surrounding pins 16, and finally pass The plastic encapsulation material 18 encapsulates the semiconductor chip 14 and the pin 16. The existing packaging process can only realize the packaging of a single semiconductor chip and pin, and the encapsulation efficiency is low. In addition, the pins 16 are arranged around the semiconductor chip 14, and the pads 15 on the semiconductor chip 14 need to be electrically connected to the surrounding pins 16 through metal wires 17, so that the volume occupied by the entire packaging structure is relatively large. , which is not conducive to the improvement of the integration degree of the packaging structure.

[0025] For this reason, the presen...

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Abstract

A packaging structure comprises a lead frame, a pre-packaging face plate. The lead frame is provided with a plurality of bearing units distributed in a matrix mode and middle ribs used for fixing the bearing units, each bearing unit comprises a plurality of independent pins, and openings are formed between adjacent pins. The pre-packaging face plate comprises a first plastic-packaging layer, openings, and a second plastic-packaging layer, wherein a plurality of integration units distributed in a matrix mode are arranged in the first plastic-packaging layer, at least one semiconductor chip is arranged in each integration unit, a plurality of welding discs are arranged on the surface of the semiconductor chip, the welding discs are provided with metal protruding blocks, the pre-packaging face plate is inversely arranged on the first surface of the lead frame, the integration units correspond to the bearing units, the metal protruding blocks on the semiconductor pins are connected with the first surfaces of the pins in a welding mode. The openings are filled into the openings between the pins, the second plastic-packaging layer is filled into the space between the pre-packaging face plate and the first surface of the lead frame, and the second plastic-packaging layer is exposed of the second surfaces of the pins. The packaging structure is small in occupied space, and the integration level is improved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a packaging structure. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive BGA (BallGridArray) and other packaging forms, new packaging technologies that have developed rapidly in recent years, such as Quad Flat No-lead QFN (QuadFlatNo-leadPackage) packaging, due to its good thermal performance and electrical performance, small size Many advantages, such as low cost and high productivity, have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a structural schematic diagram of an existing QFN ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/495
CPCH01L24/97H01L2224/48091H01L2224/16245H01L2224/48247H01L2924/15788H01L2924/00014H01L2924/00
Inventor 陶玉娟
Owner NANTONG FUJITSU MICROELECTRONICS
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