Layout design photoetching technology friendliness detection method based on regular figure filtering

A lithography process and layout design technology, which is applied in the directions of photolithography process exposure devices, microlithography exposure equipment, etc., can solve the problem of long software calculation and use time, unfavorable layout design, lithography process friendliness, application and production cost of inspection kits Advanced problems, to achieve good matching, fast and accurate search, and reduce the cost of use

Active Publication Date: 2015-07-08
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Although this method can accurately find process hotspots, the software calculation and use time of the whole process will be very long, and the corresponding production costs will be relatively high, and it is not conducive to the foundry's layout design photolithography process friendliness inspection kit. application

Method used

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  • Layout design photoetching technology friendliness detection method based on regular figure filtering
  • Layout design photoetching technology friendliness detection method based on regular figure filtering
  • Layout design photoetching technology friendliness detection method based on regular figure filtering

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Experimental program
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Effect test

Embodiment 1

[0044]Figure 3(a) to Figure 3(f) are an embodiment of filtering the original target graphic data in the layout design lithography process friendliness inspection method based on regular graphic filtering according to the present invention, combined with Figure 3(a) to Figure 3 3(f), this embodiment is a method of filtering the original data by using the graphics around the edge fragment near the vertex of the convex angle in the original target graphics data, the filtering method described in this embodiment can be used Look for potential process hotspots such as Line Pinch, Line Bridge, and Hole Overlap Missing.

[0045] For example, filtering raw target pattern data to find potential process hotspots with bad connections. FIG. 3( a ) is a design pattern of part M1 (first metal wiring), including a first connection layer ( M1 ) 11 , a contact hole ( CONTACT ) 12 and a first via layer ( VIA1 ) 13 . As shown in Figure 3(b), select all the cut edges 14 of the convex corner vert...

Embodiment 2

[0047] Figure 4(a) to Figure 4(e) are another embodiment of filtering the original target graphic data in the layout design lithography process friendliness inspection method based on regular graphic filtering according to the present invention, combined with Figure 4(a) ~ Figure 4(e), this embodiment is a method of filtering the original target graphic data by using the graphics around the edge fragment near the concave corner vertex. This method can be used to find Line Pinch and Process hotspots such as Line Bridge.

[0048] FIG. 4( a ) is a design pattern of a small part of M1 (first metal wiring), including the first connection layer 11 (M1). As shown in Figure 4(b), first select all the trimming edges 22 near the vertex of the concave angle, wherein the length of the trimming edges 22 can be 0.5 times the minimum design size of the gap (space), preferably 0.4 to 0.45 times, This keeps two adjacent cut edges from spanning the entire gap width. Then, select the limited s...

Embodiment 3

[0050] Figures 5(a) to 5(g) are yet another embodiment of filtering the original target graphic data in the layout design lithography process friendliness inspection method based on regular graphic filtering according to the present invention, combined with Figure 5(a) ~ Fig. 5(g), this embodiment uses the graph around the edge fragment near the apex of the concave corner to filter the raw data, which can be used to find the channel length of the transistor caused by the short-extended L-shaped design Or a filtering method for the potential process hotspot area of ​​channel width unevenness. This process hot spot will affect the electrical performance of the device or even fail, especially for short-channel transistors.

[0051] FIG. 5( a ) is a plane design of a small part of transistors, including a polycrystalline layer (Poly) 31 and an active area (Active Area) 32 . As shown in FIG. 5( b ), the gate region 33 is selected first, where the width of the active region is calle...

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Abstract

The invention provides a layout design photoetching technology friendliness detection method based on regular figure filtering. According to the layout design photoetching technology friendliness detection method based on regular figure filtering, by adding a step of filtering original object figure data before steps of performing optical proximity effect correction and technological error figure simulation, the time consumption of layout design photoetching technology friendliness detection is shortened, the usage cost of software and hardware is reduced, and also the extremely good matching between a detection result and a method of prior art can be realized, and thus the rapid accurate search for technological hot-spot areas in layout design is realized.

Description

technical field [0001] The invention relates to the field of graphic design for manufacturability (DFM, Design For Manufacture), in particular to a method for checking friendliness of layout design photolithography process based on regular graphic filtering. Background technique [0002] In the current integrated circuit production process, the mask plate is first made according to the designed layout, and then the pattern on the mask plate is transferred to the wafer through photolithography technology. Due to the limitation of optical proximity effect (OPE) in subwavelength lithography technology Affected, when the layout of the mask plate is finally transferred to the wafer, there will be a large distortion. Although various resolution enhancement techniques (RET), such as optical proximity correction (OPC), phase shift mask (PSM), etc., can be used to improve the precision of lithography, due to improper design or limitations of RET technology itself, the final crystal ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G03F7/20
Inventor 王伟斌朱忠华魏芳张旭升
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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