Manufacturing method of semiconductor device

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as immature technology, etching loading, complexity, etc., to ensure critical dimensions, improve performance, and avoid size reduction Effect

Active Publication Date: 2014-05-21
SEMICON MFG INT (SHANGHAI) CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although in the prior art, there are some improvement schemes for the above problems, such as using BARC, DBARC (developer-soluble bottom anti-reflective coating), TARC, etc. under the photoresist used to form the ion implantation masking layer, and the application OPC (Optical Proximity Correction, Optical Proximity Correction), etc. However, these solutions have certain problems, such as high cost and etching loading problems in the application of BARC technology, DBARC technology is not yet mature, and TARC can improve the CD uniformity of semiconductor substrates It is not helpful, and the technology of applying OPC technology to semiconductor substrates is not mature and the process is relatively complicated, etc.
[0005] Therefore, it is necessary to propose a new manufacturing method for semiconductor devices to solve the above-mentioned problem that the reflected light below the ion implantation shielding layer affects the critical dimensions of the ion implantation shielding layer, and improve the performance of semiconductor devices

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Embodiment Construction

[0035] In the following description, a lot of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described.

[0036] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented here. On the contrary, the provision of these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the drawings, the proportions of components (layers, regions, etc.) do not represent the actual sizes and proportions of the components; for clarity, the sizes and relative sizes of layers and regions may be...

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Abstract

The invention provides a manufacturing method of a semiconductor device, and relates to the semiconductor technical field; the method comprises the following steps: S101, providing a semiconductor substrate; S102, forming an antireflective layer in a boundary between a zone wherein ion injection is to be carried out and a zone wherein an ion implantation shielding layer is to be formed on the semiconductor substrate; S103, employing photoresist to form the ion implantation shielding layer on the semiconductor substrate. The manufacturing method of the semiconductor device adds the step in which the antireflective layer is formed in a boundary between the zone wherein ion injection is to be carried out and the zone wherein the ion implantation shielding layer is to be formed; in a process to expose a photoresist film so as to form the ion implantation shielding layer, the reflection light from the semiconductor substrate can be prevented or stopped from entering the photoresist film, so the reflection light cannot cause size reduction of the ion implantation shielding layer, thereby ensuring key size of the ion implantation shielding layer, and improving performance of the semiconductor device.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a method for manufacturing a semiconductor device. Background technique [0002] In the field of semiconductor technology, with the rapid development of nanofabrication technology, the feature size of transistors has entered the nanoscale. As the device size continues to decrease, the critical dimension (CD) and overlay tolerance of the ion implantation shielding layer (IMP block layer) are also rapidly shrinking to meet the ever-decreasing device size. need. [0003] Correspondingly, the reflectivity and morphological changes of the semiconductor substrate under the ion implantation shielding layer (generally photoresist) have brought more and more serious effects on the critical dimensions of the ion implantation shielding layer. Such as figure 1 As shown, in the existing semiconductor device manufacturing process, due to the morphological characteristics of the front...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02
CPCH01L21/027H01L21/0276
Inventor 舒强胡华勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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