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Stacked gate type sonos flash memory and manufacturing method thereof

A technology of flash memory and manufacturing method, which is applied in the manufacture of stacked gate SONOS flash memory and the field of manufacturing embedded semiconductor memory chips, which can solve the problems of large area and insufficient compact structure of storage units, and achieve the effect of reducing the area

Active Publication Date: 2016-12-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The storage unit of this structure is not compact enough and has a large area

Method used

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  • Stacked gate type sonos flash memory and manufacturing method thereof
  • Stacked gate type sonos flash memory and manufacturing method thereof
  • Stacked gate type sonos flash memory and manufacturing method thereof

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Experimental program
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Embodiment Construction

[0080] The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

[0081] Such as image 3 As shown, the structure of the SONOS flash memory memory with stacked gates of the present invention includes a selection transistor and a storage transistor: the storage transistor is composed of an ONO layer and a first polysilicon gate from bottom to top; an ONO (oxide-nitride-oxide) layer structure is adopted (From bottom to top: oxide layer: Nitride layer: Oxide layer: ), above the ONO layer is the first polysilicon gate;

[0082] The second polysilicon gate constitutes the selection transistor, and the gate oxide of the selection transistor is a medium-voltage oxide layer ( left and right); there is silicon nitride above the selection tube (that is, silicon nitride on the silicon gate, and its thickness is );

[0083] There is a certain overlap between the storage tube and the selection tube, and the ...

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PUM

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Abstract

The invention discloses a structure of a stacked gate type SONOS flash memory. The memory is composed of a selection tube and a storage tube. The storage tube is composed of an ONO layer and a first polysilicon gate from bottom to top; the selection tube It consists of a medium-voltage oxide layer and a second polysilicon gate from bottom to top. The gate oxide of the selector tube is a medium-voltage oxide layer. There is silicon nitride above the selector tube; the first polysilicon gate and the third polysilicon gate. There are silicon nitride sidewalls on the side walls of the second polysilicon gate; there is a certain overlap between the storage tube and the selection tube, and the overlap amount is X, 0<X≤the width of the first polysilicon gate. In addition, the invention also discloses a manufacturing method of the stacked gate SONOS flash memory. The present invention can effectively reduce the area of ​​the memory unit.

Description

technical field [0001] The invention belongs to a semiconductor process method in a semiconductor integrated circuit, in particular to a method for manufacturing an embedded semiconductor memory chip, in particular to a method for manufacturing a stacked gate type SONOS flash memory. Background technique [0002] figure 1 A schematic diagram of the existing storage tube structure, such as figure 1 As shown, the ONO layer and the polysilicon gate form the storage tube, and the medium-voltage oxide layer and the polysilicon gate form the selector tube. The storage unit of this structure is not compact enough and has a relatively large area. [0003] Such as Figure 2A-Figure 2Q As shown, the existing figure 1 The technological realization process of the storage tube structure shown generally adopts the following steps: [0004] 1. Forming isolation regions and active regions; [0005] 2. Medium and low voltage wells and threshold voltage adjustment plasma implantation,...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/115H01L21/8247H01L29/423H10B69/00
Inventor 张可钢陈广龙陈华伦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP