Interconnection structure and manufacture method thereof

Abstract

The invention discloses an interconnection structure. The interconnection structure comprises a lower wiring structure which is located on a substrate, a shielding layer which is located on the lower wiring structure, and an upper wiring structure which is located on the shielding layer, wherein the shielding layer comprises grapheme. According to the interconnection structure and a manufacture method thereof, which are provided by the invention, the grapheme which is a single crystal thin conductive material is used as the shielding layer between upper and lower metal connecting lines; the connecting line noise of a small size device is effectively reduced; and the signal accuracy of the device is improved.

Description

technical field [0001] The invention relates to an interconnect structure and a manufacturing method thereof, in particular to a back-end process using single-layer or multi-layer graphene and a manufacturing method thereof. Background technique [0002] As integrated circuits enter the nanoscale range, the crosstalk between the back-end interconnect lines has become one of the important factors that plague circuit design. Crosstalk is the coupling between two signal lines, the mutual inductance and mutual capacitance between the signal lines cause noise on the line. Inductive noise generated by crosstalk can affect signal integrity and chip performance in many ways. For example, when the victim signal is in steady state 0 or steady state 1, glitch interference will be generated. Usually the signal transition time in the circuit is much shorter than the steady-state time, because most signals are often in a steady state, and the glitch noise will destroy this steady state. ...

AI Technical Summary

Problems solved by technology

However, these four methods face greater difficulties at the nanoscale, or will reduce the performance parameters of the chip.

Inserting a buffer in a high-speed circuit will damage and reduce the operating frequency of the chip, changing the wiring spacing, adopting twice the wiring spacing and changing the size of the gate circuit will increase the occupied wiring resources, and the traditional shielding of the victim node will make the wiring more complicated. , it is more difficult to use ordinary EDA tools for wiring, and it also increases the cycle and cost of research and development

[0004] At the same time, there will be electromigration when using traditional metal wires

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