Low power consumption SRAM (Static Random Access Memory) unit circuit structure

Abstract

The invention discloses a low power consumption SRAM (Static Random Access Memory) unit circuit structure which comprises a latch composed of four MOS (Metal Oxide Semiconductor) pipes. Gating pipes are arranged on the two sides of the latch, one end of the latch is connected with a power supply through a writing spool, and the other end of the latch is grounded through an inverted signal pipe. Reading to stored data can be accomplished through two additional pull-down pipes. The circuit in the invention is simple and easy to control. The working voltage of the entire circuit can be lowered to be the same as that of a common digital logic circuit, so that the work power consumption is lowered greatly. Requirements on the driving capability of the SRAM writing circuit are lowered, and related circuit design is simplified. Requirements to a sense amplifier of an SRAM reading circuit are lowered, and the related circuit design is simplified.

Description

technical field [0001] The invention relates to the field of static memory, in particular to a low power consumption SRAM unit circuit structure. Background technique [0002] The static memory (SRAM) in the CMOS integrated circuit process is generally composed of 6 tubes. This structure has a small area, but because this unit will be disturbed when reading and writing, it puts forward higher requirements on the working voltage. , has become a difficulty in reducing the operating voltage and power consumption in the integrated circuit SOC. [0003] refer to figure 1 As shown, the most common SRAM storage unit is composed of 6 MOS, WL represents the word line, and BL / BLB represents the bit line. When reading, WL is turned on, and the bit line whose storage terminal is "0" will be pulled down slowly. When the voltage difference between BL and BLB reaches a certain value, the sense amplifier will read out the data. This memory cell will have some interference and contention ...

AI Technical Summary

Problems solved by technology

[0005] The existing SRAM unit composed of 6 MOSs, when writing, the Pass gate connected to WL will compete with the pull-up PMOS, when reading, WL is turned on, and the transmission tube will form a partial voltage with the pull-down tube to make "0" The higher the value, the lower the static noise margin, which makes the operating voltage of the traditional 6T SRAM not too low, which is the bottleneck of reducing the operating voltage of the entire chip and the bottleneck of reducing power consumption.

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