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Method and device for background digital calibration of production line ADC (analog-to-digital converter)

A technology of calibration device and calibration method, applied in the direction of analog/digital conversion calibration/test, etc., can solve the problems of limited application range and difficult synchronization of output signals, achieve small calibration error, overcome accuracy drop and large error, and high accuracy Effect

Active Publication Date: 2014-08-06
SOUTH CHINA UNIV OF TECH
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  • Abstract
  • Description
  • Claims
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Problems solved by technology

However, it is difficult to achieve complete synchronization of two different frequency output signals, which will bring large errors to the reference ADC calibration method during the calibration process, thus limiting the application range of the method

Method used

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  • Method and device for background digital calibration of production line ADC (analog-to-digital converter)
  • Method and device for background digital calibration of production line ADC (analog-to-digital converter)
  • Method and device for background digital calibration of production line ADC (analog-to-digital converter)

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Embodiment

[0044] Such as figure 1 As shown, this embodiment discloses a background digital calibration device of a pipeline ADC, including an adaptive filter, a high-precision ADC redundant sub-stage, a data selection module, a data distribution module, a multi-way switch module and a control signal generation module; The precision of the high-precision ADC redundant sub-stage used in this embodiment is higher than that of each ADC sub-stage in the pipeline. All components of the calibration device in this embodiment are realized by CMOS technology. The adaptive filter used in this embodiment is an LMS adaptive filter, and of course other adaptive filters such as RLS may also be used. The pipeline ADC includes n-level ADC sub-stages, which are respectively the first stage to the n-th stage; the analog signal is input to the first-stage ADC sub-stage after passing through the sample-and-hold amplifier SHA. In this embodiment, the channels of the data selection module are respectively m...

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Abstract

The invention discloses a method and a device for background digital calibration of a production line ADC (analog-to-digital converter). The device comprises an adaptive filter, a high-precision ADC redundancy sublevel, a data selection module, a data distribution module, a multiway switch module and a control signal generation module. The method includes: firstly, the control signal generation module controls the data selection module, the data distribution module and the multiway switch module, and the high-precision ADC redundancy sublevel and the adaptive filter perform initialization calibration sequentially from the first level to the j level of the production line ADC to enable the production line ADC to operate in a high-precision output state; secondly, during normal operation of the production line ADC, the control signal generation module controls each module to perform random calibration from the first level to the j level of the production line ADC so as to prevent ADC performance reduction resulted from an external environment and an internal environment of a chip. The method and the device for background digital calibration of the production line ADC have the advantages of small calibration errors and high calibration precision.

Description

technical field [0001] The invention relates to a calibration device in the technical field of microelectronics, in particular to a background digital calibration device and method for pipeline ADCs. Background technique [0002] Pipeline ADC (Analog-to-Digital Converter) is the interface between the external analog world and electronic systems. It is the mainstream structure of high-speed and high-bit ADCs. It has the characteristics of high speed and high precision. It is used in high-resolution image processing, video processing and wireless communication. And other fields have been widely used, becoming one of the current ADC research hotspots. However, when the accuracy of the pipeline ADC reaches more than 12 bits, errors caused by various factors such as capacitance mismatch, parasitic capacitance at the input of the operational amplifier, charge injection, comparator offset, and process deviation seriously limit the performance of the ADC. Traditional analog circuit...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/10
Inventor 李斌燕振华吴朝晖
Owner SOUTH CHINA UNIV OF TECH
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