Copper metallization structure of power semiconductor chip and preparation method thereof
A power semiconductor and copper metal technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problem of high power applied to the bonding point, increase, and increase the difficulty and cost of the metallization process, etc. problems, to achieve the effect of reducing process difficulty and cost, ensuring life and reliability, and enhancing mechanical strength
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Embodiment 1
[0062] combine figure 1 The copper metallization structure of the power semiconductor chip provided by Embodiment 1 of the present invention will be described.
[0063] like figure 1 As shown, the copper metallization structure of the power semiconductor chip provided by Embodiment 1 includes: a barrier layer 102 located above the substrate 101, a seed copper layer 103 located above the barrier layer 102, and an enhancement layer 104 located above the seed copper layer 103, Copper metallization layer 105 over enhancement layer 104 .
[0064]Wherein, from the perspective of improving the mechanical strength of the copper metallization structure, preferably, the enhancement layer 104 covers the entire surface of the seed copper layer 103, but since the current conduction capability of the enhancement layer 104 is smaller than that of copper, Therefore, in order to ensure the current conduction capability of the electrode, the enhancement layer 104 with a smaller area should be...
Embodiment 2
[0111] The copper metallization structure of the power semiconductor chip described in the second embodiment has many similarities with the copper metallization structure described in the first embodiment, and the only difference is that the position of the enhancement layer in the entire copper metallization structure is different. For the sake of brevity, this embodiment only focuses on the description of the differences, and for the similarities, please refer to the description of the first embodiment.
[0112] Such as Figure 5 As shown, the copper metallization structure of the power semiconductor chip described in Embodiment 2 includes: a barrier layer 502 located above the substrate 501, and an enhancement layer 504 located above the barrier layer 502, wherein the enhancement layer 504 covers the barrier layer 502 The copper metallization structure further includes a copper seed layer 503 located above the enhancement layer 504 and the barrier layer 502 not covered by t...
Embodiment 3
[0124] The copper metallization structure of the power semiconductor chip described in the third embodiment has many similarities with the copper metallization structure described in the first embodiment, and the only difference is that the position of the enhancement layer in the entire copper metallization structure is different. For the sake of brevity, this embodiment only focuses on the description of the differences, and for the similarities, please refer to the description of the first embodiment.
[0125] combine Figure 7 The copper metallization structure of the power semiconductor chip provided by Embodiment 3 of the present invention is introduced.
[0126] Such as Figure 7 As shown, the copper metallization structure of the power semiconductor chip described in the third embodiment includes: a barrier layer 702 located above the substrate 701 , a seed copper layer 703 located above the barrier layer 702 , and a copper metallization located above the seed copper ...
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Abstract
Description
Claims
Application Information
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