Semiconductor device including hemt and misfet and method of forming same

A semiconductor, III-V technology, used in semiconductor devices, semiconductor/solid state device manufacturing, transistors, etc.

Active Publication Date: 2017-03-01
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Despite the compelling properties shown above, there are still multiple challenges associated with the development of III-V semiconductor compound-based devices.

Method used

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  • Semiconductor device including hemt and misfet and method of forming same
  • Semiconductor device including hemt and misfet and method of forming same
  • Semiconductor device including hemt and misfet and method of forming same

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Embodiment Construction

[0030] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable concepts that can be implemented in a wide variety of specific contexts. The specific embodiments discussed are illustrative only, and do not limit the scope of the invention.

[0031] A plurality of semiconductor chip regions are marked on the substrate by dicing lines lying between the chip regions. The substrate will undergo various steps of cleaning, layering, patterning, etching and doping steps to form the integrated circuit. The term "substrate" here generally refers to a bulk substrate on which layers and device structures are formed. In some embodiments, the bulk substrate includes silicon or a compound semiconductor such as GaAs, InP, Si / Ge, or SiC. Examples of these layers include dielectric layers, doped layers, polysilicon layers, diffusion barrier layers or conductive layers. ...

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Abstract

The present invention relates to semiconductor devices including HEMTs and MISFETs and methods of forming the same, which include a first III-V compound layer. The second III-V compound layer is disposed on the first III-V compound layer and is compositionally different from the first III-V compound layer. A third III-V compound layer is deposited on the second III-V compound layer and is compositionally different from the second III-V compound layer. Source features and drain features are disposed in each MISFET and HEMT region on the third III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A gate dielectric layer is disposed under the gate electrode in the MISFET region but over the top surface of the third III-V compound layer.

Description

technical field [0001] The present invention relates generally to semiconductor structures, but more particularly to combined high electron mobility transistor (HEMT) and metal insulator semiconductor field effect transistor (MISFET) structures and methods of forming such semiconductor structures. Background technique [0002] In semiconductor technology, due to their properties, Group III-V (or III-V) semiconductor compounds are used to form various integrated circuit devices, such as high-power field-effect transistors, high-frequency transistors, or high-electron-mobility transistors ( HEMTs). Like a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a HEMT is a junction (i.e., a heterojunction) that incorporates a channel between two materials with different bandgaps as an alternatively doped region field effect transistors. Compared with MOSFETs, HEMTs have several attractive properties, including high electron mobility, ability to transmit signals at high fr...

Claims

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Application Information

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Patent Type & AuthorityPatents(China)
IPC IPC(8): H01L27/06H01L29/06H01L21/8234H01L21/335
CPCH01L29/517H01L29/66462H01L29/7786H01L29/1066H01L29/2003H01L27/0605H01L27/085H01L21/8252H01L29/66431H01L29/778H01L29/66522H01L27/088
Inventor周仲彦刘圣得杨富智刘世昌蔡嘉雄
OwnerTAIWAN SEMICON MFG CO LTD