Copper interconnection structure and method for manufacturing same
A technology of copper interconnection structure and manufacturing method, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., capable of solving problems such as cracks in the interlayer dielectric layer 101, low mechanical strength, and cracking of the interlayer dielectric layer 101 , to achieve the effect of preventing fracturing, avoiding direct contact, and reliable semiconductor structure
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Embodiment 1
[0049] This embodiment provides a copper interconnection structure on the top layer. Generally, in the copper interconnection structure on the top layer, the thickness of the copper interconnection line can reach 16000 angstroms, while in the copper interconnection structure between layers, the thickness of the copper interconnection line is The thickness is only about 3000 angstroms, so the copper interconnection structure on the top layer is more likely to prevent the crack problem mentioned in the background art. It should be noted that the technical solution of the present invention is not only applicable to the copper interconnection structure of the top layer, but also applicable to the interlayer copper interconnection structure, so the structure disclosed in this embodiment below can be applied to the interlayer copper interconnection structure. In the interconnection structure, similarly, the structures and manufacturing methods described in the second to fourth embodi...
Embodiment 2
[0057] This embodiment continues to provide a top layer copper interconnection structure. The copper interconnection structure provided in this embodiment has many similarities with the copper interconnection structure described in Embodiment 1. For the similarities, please refer to the corresponding content in Embodiment 1. This embodiment focuses on the differences between the two to be explained.
[0058] Please refer to Image 6 , the copper interconnection structure includes a semiconductor substrate (not shown), a first interlayer dielectric layer 611 located on the semiconductor substrate, a copper plug 631 penetrating through the first interlayer dielectric layer, located on the The second interlayer dielectric layer 612 on the first interlayer dielectric layer 611 runs through the copper interconnection line 632 of the second interlayer dielectric layer 612 . In this embodiment, a barrier layer 613 is further included between the first interlayer dielectric layer 61...
Embodiment 3
[0065] This embodiment provides a method for fabricating a top-layer copper interconnection structure, including steps S31 to S38. It should be noted that in this embodiment, the steps are named from S31 to S38 to distinguish and facilitate description of the steps, but the sequence of the steps is not limited, and the sequence of the steps can be adjusted in different embodiments. Each step will be explained below, please refer to Figure 5 as well as Figure 7 to Figure 13 .
[0066] Step S31, providing a semiconductor substrate.
[0067] The semiconductor substrate provided in this embodiment refers to a semiconductor substrate that can include various types of semiconductor device structures. Although it is not shown in the figure, those skilled in the art can think that the semiconductor substrate can include the semiconductor substrate that can be fabricated in the field. Any structure on the semiconductor substrate, such as CMOS and other device structures.
[0068]...
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