Shift register unit, gate drive circuit and display device

Abstract

The invention discloses a bidirectional scanning gate drive circuit and a shift register unit of the bidirectional scanning gate drive circuit. The shift register unit comprises a first input end (1), a second input end (2), a first clock end (6) and an output end (8). A shift trigger signal and a reset signal are connected into the first input end (1) and the second input end (2) respectively. When forward shift and backward shift are switched, the signals connected into the first input end (1) and the second input end (2) are switched; a clock signal is connected into the first clock end (6), and the clock signal is used for providing drive level for the output end (8). The circuit of the shift register unit can be composed of at least four transistors and one capacitor. The circuit of the shift register unit is simple in structure, and the problem of coupled noise voltage caused by the clock signal can be solved.

Description

technical field [0001] The invention belongs to the technical field of circuit driving, and in particular relates to a shift register unit, a gate drive circuit (gate drive IC) and a display device using the shift register unit. Background technique [0002] The driving circuit of the display device mainly includes a gate driving circuit (scanning driving circuit) and a data driving circuit (or source driving circuit), wherein the gate driving circuit includes cascaded shift register units, and the input clock signal CLK is shifted After the conversion of the register unit, it will be sequentially added to the gate line of each pixel row of the display device, so as to control the display of the display device row by row. [0003] The circuit of the existing shift register unit such as figure 1 As shown, it includes four transistors and two capacitors, that is, a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor C. ...

AI Technical Summary

Problems solved by technology

[0010] The disadvantage of this shift register unit is that the fourth transistor M4 applies a high level for a very short time, and will not drift under the DC bias voltage. Most of the time, PU and OUTPUT are in a floating state, which is easy for other parasitic Capacitance, etc., resulting in misoperation

This will lead to uneven brightness of the display device and affect the quality of the product

At the same time, this kind of shift register unit cannot realize bidirectional scanning, and the clock signal CLK will generate coupling (Coupling) noise voltage

Images