P-type fin field effect transistor and method of forming the same

Abstract

Provided are a P-type fin-type field effect transistor and a forming method thereof. The P-type fin-type field effect transistor comprises a semiconductor substrate, the semiconductor substrate is provided with a protruded fin part, a side wall and the top surface of the fin part are provided with gate structures, side walls of the gate structures are provided with lateral walls, the fin parts on two sides of the gate structures are provided with grooves, side walls and the bottom surfaces of the grooves are provided with silicon germanium layers, the surface of each silicon germanium layer is provided with a barrier layer, the barrier layer is provided with a metal layer, and the metal layer is filled with grooves, and the metal layer, the barrier layer and the silicon germanium layers form a source region / drain region of the P-type fin-type field effect transistor. The silicon germanium layers on the fin parts of the adjacent fin-type field effect transistors are not subject to bridging.

Description

Technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a P-type fin field effect transistor and a method for forming the same. Background technique [0002] The MOS transistor generates a switching signal by applying a voltage to the gate and adjusting the current through the channel region. However, when semiconductor technology enters the node below 45 nanometers, the traditional planar MOS transistor's ability to control channel current becomes weak, causing serious leakage current. Fin FET is an emerging multi-gate device. It generally includes a semiconductor fin with a high aspect ratio, and a gate structure covering part of the top and sidewalls of the fin. The source and drain regions in the fins on both sides of the pole structure. [0003] In order to improve the performance of fin-type field effect transistors, in the manufacturing process of fin-type field-effect transistors, stress layers are usually formed on the s...

AI Technical Summary

Problems solved by technology

[0004] The silicon germanium layer 104 is usually formed by a selective epitaxial process, but in the epitaxial process, the growth rate of the semiconductor material on different crystal planes is different, for example, the growth rate of the silicon material on the (111) crystal plane is lower than that of other crystal planes. The growth rate causes the shape of the subsequently formed silicon germanium layer 104 to be different from the rectangular shape of the source / drain region 103, for example figure 1 The cross section of the silicon germanium layer 104 is a rhombus

[0005] Please refer to figure 2 , with the reduction of the size of the semiconductor process, the distance between the two fins 102 in the fin field effect transistor is getting closer and closer, and the shape of the silicon germanium layer 104 is irregular, which may cause the fins located on the adjacent fins 102 The silicon germanium layer 104 is bridged to form a contact region 105, causing leakage current

[0006] Therefore, the silicon germanium layers 104 of two adjacent fin field effect transistors in the prior art are easy to contact, causing leakage current, and the stress of the silicon germanium layer 104 formed in the prior art is relatively small

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