Forming method of fin field effect transistor

Abstract

The invention discloses a forming method of a fin field effect transistor. The forming method comprises the steps of providing a semiconductor substrate which is provided with at least two adjacent convex fin parts, a grid electrode structure crossing top and side wall surfaces of the fin parts and source/drain areas located in the fin parts on the two sides of the grid electrode structure, performing selective epitaxy on the source/drain areas to form semiconductor layers which cover partial side wall and top surfaces of the fin parts, forming a sacrificial layer covering the surfaces of the semiconductor substrate, the fin parts and the semiconductor layers, etching back the sacrificial layer, exposing partial surfaces of the semiconductor layers, forming mask layers on the exposed surfaces of the semiconductor layers, and etching to remove partial edges of the sacrificial layer and the semiconductor layers by taking the mask layers as masks, wherein the semiconductor layers located above the tops of the fin parts are provided with bulges, and the semiconductor layers located on the two sides of the fin parts are provided with edges. The forming method can effectively avoid bridging of embedded sources/drains of the connected fin parts, and can improve the stability of a device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor. Background technique [0002] MOS transistors generate switching signals by regulating the current through the channel region by applying a voltage to the gate. However, when the semiconductor technology enters the node below 45 nanometers, the control ability of the traditional planar MOS transistor on the channel current becomes weak, causing serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a semiconductor fin with a high aspect ratio, a gate structure covering part of the top and side walls of the fin, and a gate structure located on the gate Source and drain regions in the fins on both sides of the pole structure. [0003] During the fabrication process of the FinFET, an embedded source region and a drain region (Embedded source / drain) are u...

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Problems solved by technology

[0004] The embedded source/drain region 104 is usually formed by a selective epitaxial process, but in the epitaxial process, the growth rate of semiconductor materials on different crystal planes is different, for example, the growth rate of silicon material on the (111) crystal plane is slower than that of other crystal planes. The growth rate of the crystal plane causes the shape of the subsequently formed embedded source/drain region 104 to be different from the rectangular shape of the source/drain region 103, for example figure 1 The cross section of the embedded sourc...

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