Semiconductor structure and forming method thereof

Abstract

Provided are a semiconductor structure and a forming method thereof. The forming method comprises the steps that a semiconductor layer is formed in a source region and a drain region of a first fin part, covers the top surface and part of the side wall surface of the first fin part and is provided with protruded first ridge corners and second ridge corners, the first ridge corners are located on the top surface of the first pin part, and the second ridge corners are located on the surface of a side wall of the first fin part; a barrier layer is formed on a substrate, the first fin part and the surface of the semiconductor layer and fills a space between the adjacent second ridge corners, so that the adjacent second ridge corners are connected through the barrier layer; a dielectric layer is formed on the surface of the barrier layer, a first opening in the dielectric layer is exposed out of the barrier layer on the surfaces of at least two adjacent first ridge corners, the position of a side wall of the first opening in contact with the barrier layer is higher than the horizontal positions of the second ridge corners; the barrier layer at the bottom of the first opening is etched until the barrier layer is exposed out of the surface of the semiconductor layer, and a first conductive layer is formed on the surface of the semiconductor layer in the first opening. The performance of a formed semiconductor device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short channel effect of the transistor and suppress the leakage current, the prior art proposes a Fin Field Effect Tra...

AI Technical Summary

Problems solved by technology

[0006] However, although the tensile stress can improve the performance of the NMOS transistor, the first conductive layer 104 will also provide the tensile stress to the first fin portion 102, correspondingly reducing the carrier mobility in the channel region of the PMOS transistor, which is still very important for improving the performance of the semiconductor transistor. Device performance hindered

Images