Conductive plug and TSV forming method

Abstract

The invention provides a conductive plug and TSV forming method. The conductive plug forming method includes the steps that a blind hole is formed in a semiconductor substrate, after metal layers are formed in the blind hole and formed on the semiconductor substrate, the metal layer, of the part of the full thickness, on the semiconductor substrate is removed first, and the substrate is heated by adopting the annealing technology, so that refinement, regrowth and homogenization of crystalline grains in the metal layers are achieved, and the internal structure of the metal layers is optimized. After the metal layer, of the part of the full thickness, on the semiconductor substrate is removed, while stress generated by deformation of the metal layers in the annealing process can be effectively reduced, stress generated by volume deformation, based on heat-expansion and cold-contraction, of the semiconductor substrate and structures on all the layers on the semiconductor substrate is fully released, acting force between the substrate and the structures on all the layers is reduced, and cracks on the connection faces between the semiconductor substrate and the structures on all the layers in the semiconductor substrate are avoided.

Description

technical field [0001] The invention relates to the field of semiconductor formation, in particular to a method for forming a conductive plug and a TSV. Background technique [0002] With the rapid development of the information industry, the feature size (CD) of integrated circuits has been continuously reduced, and the manufacturing process of integrated circuit chips has also been miniaturized. The development of integrated circuit chip preparation technology has prompted integrated circuit packaging technology to continuously pursue the demand for higher performance, more functions, smaller size, lower power consumption and cost. [0003] In the development of integrated circuit packaging technology, 3D TSV (Through-Silicon-Via) packaging technology realizes the interconnection between chips by making vertical conduction between chips and between wafers. of the latest technology. Compared with the previous IC package bonding and overlay technology using bumps, TSV can ...

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Problems solved by technology

[0006] However, in actual operation, it is found that after the annealing process, the connection interface between the metal conductive layer 14 and the insulating layer 12, and even between the insulating layer 12 and the substrate 10, cracks of varying degrees will appear, thereby affecting the conductive stability of the formed TSV. , and the stability of the resulting semiconductor device

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