Decimal and integer frequency divider circuit and implementation method thereof

Abstract

The invention discloses a decimal and integer frequency divider circuit and an implementation method of the decimal and integer frequency divider circuit. The decimal and integer frequency divider circuit comprises an orthogonal clock generation module, a pulse swallowing circuit, a divide-by-2 divider, a mode control module and a clock selection module. The method includes the steps that firstly, an initial clock generates two pairs of difference clock signals which are orthogonal through the orthogonal clock generation module; secondly, a MODE signal generates a pulse swallowing control signal through the mode control module, and the number of pulse swallowing times is determined; thirdly, the clock selection module selects an output clock. According to the decimal and integer frequency divider circuit, the frequency division of different integer and decimal frequency division factors can be achieved by programming the MODE control signal and the clock selection signal, and the decimal and integer frequency divider circuit has the advantages of being high in frequency resolution, wide in frequency division factor range and high in module repeated utilization rate. The frequency divider is suitable for the field of programmable decimal frequency division phase-locked loop design, frequency synthesizer design and other clock system design.

Description

technical field [0001] The present invention mainly relates to the field of clock system design, and can be applied to fractional frequency division phase-locked loops and frequency synthesizers in radio frequency transceivers, in particular to a fractional-integer frequency divider circuit and its implementation method, so that the fractional frequency division frequency Synthesizer design implementation is easier and faster. Background technique [0002] As a key module in the field of radio frequency communication, the frequency synthesizer mainly provides the high-frequency carrier signal for the transmitting system, and at the same time realizes the frequency modulation function, and realizes the frequency modulation from the low-frequency digital signal to the high-frequency signal; for the receiving system, the frequency synthesizer is mainly for It provides precise local oscillator signals with frequency spacing consistent with that of the transmitting system. [00...

AI Technical Summary

Problems solved by technology

However, the use of a smaller frequency reference clock means that the loop bandwidth of the frequency synthesizer needs to be reduced accordingly, resulting in a longer loop lock time; The phase noise suppression ability of the oscillator VCO is not enough, which reduces the phase noise performance of the frequency synthesizer; if a large frequency division factor N is used, the phase noise contribution will be proportional to other sub-modules of the frequency division factor N (such as frequency and phase detectors) , charge pump, etc.) will also degrade the noise performance of the frequency synthesizer

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