Power source clamping electrostatic discharge protective circuit

Abstract

The invention discloses a power source clamping electrostatic discharge protective circuit. The circuit comprises a transient trigger module, a clamping transistor switch-on module, a clamping transistor switch-off module and a clamping transistor. The instant trigger module is used for judging whether electrostatic discharge impact happens or not according to voltage pulse rising time of a power source pin VDD and issuing a response signal; the clamping transistor switch-on module is used for switching on a clamping transistor Mbig according to the response signal; the clamping transistor switch-off module is used for switching off the clamping transistor Mbig according to the response signal; and when switched on, the clamping transistor Mbig is used for discharging electrostatic charges caused by electrostatic discharge impact. According to the circuit, a current mirror and a PMOS transistor are introduced to do equivalent resistance; the area of the electrostatic discharge protective circuit is greatly reduced, and meanwhile the switching-on time of the transistor is longer; and the electrostatic charge discharging speed is higher and sufficient.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, and more specifically relates to a power supply clamp electrostatic discharge protection circuit. Background technique [0002] In CMOS integrated circuits, with the continuous improvement of the manufacturing process, the feature size of the device is continuously reduced to reduce the chip operating voltage and reduce power consumption. However, the continuous thinning of the gate oxide layer of the device leads to a decrease in the breakdown voltage. get lower. Integrated circuit chips may be subjected to different intensities of electrostatic discharge (ESD) impacts during manufacturing, packaging, and work. Bit ESD protection circuitry is integral to a successful chip. [0003] An effective ESD protection circuit structure, when the ESD impact comes, it can be opened quickly, providing a low-resistance channel for the discharge of electrostatic charges, so that a large amount o...

AI Technical Summary

Problems solved by technology

[0002] In CMOS integrated circuits, with the continuous improvement of the manufacturing process, the feature size of the device is continuously reduced to reduce the chip operating voltage and reduce power consumption. However, the continuous thinning of the gate oxide layer of the device leads to a decrease in the breakdown voltage. lower

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