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Input interface integrated circuit and input interface circuit thereof

A technology of input interface circuit and input terminal, which is applied in the direction of logic circuit connection/interface layout, etc., and can solve the problems of increasing circuit power consumption and system power consumption

Inactive Publication Date: 2015-03-04
XIAMEN FLOWCHIP ELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the input port circuit has a fixed pull-up or pull-down resistor, the input signal will generate a voltage drop through this resistor, which will cause a current, which will increase the power consumption of the circuit. When multiple input ports in the system consume current , the power consumption of the whole system will rise. For consumer electronics and other power-sensitive applications, this excess power consumption is unacceptable

Method used

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  • Input interface integrated circuit and input interface circuit thereof
  • Input interface integrated circuit and input interface circuit thereof
  • Input interface integrated circuit and input interface circuit thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] Such as figure 1 as shown, figure 1 It is a schematic diagram of an input interface circuit provided in Embodiment 1 of the present application. The input interface circuit includes: a parasitic capacitor Cp, a first resistor R1, a second resistor R2, a first MOS transistor M1, a first inverter U1 and a second inverter U2.

[0042] Wherein, the input terminal of the input interface circuit is grounded through the parasitic capacitance Cp, and at the same time connected to the drain of the first MOS transistor M1 through the first resistor R1, the source of the first MOS transistor M1 is grounded or powered, and the gate of the first MOS transistor M1 The pole is connected to the output terminal of the input interface circuit through the second inverter U2;

[0043] The input terminal of the input interface circuit is also connected to the output terminal of the input interface circuit through the second resistor R2, the first inverter U1 and the second inverter U2 in ...

Embodiment 2

[0049] The basic principle of the input interface circuit provided in this application is based on a characteristic of CMOS circuits, that is, whether it is an N-type or a P-type MOS transistor, when they are in the cut-off state, when there is a voltage drop from the drain to the source, they will The leakage current from the drain to the source is determined by the basic principle of the device. The magnitude of the leakage current is closely related to the voltage drop from the drain to the source and the temperature. Generally speaking, the larger the voltage drop from the drain to the source, the larger the leakage current, and the higher the temperature, the larger the leakage current. Due to the existence of this leakage current, the charge accumulated on the drain of the MOS transistor will be converted into leakage current and released to the source. The voltage drop from the drain level to the source level will decrease, which is a slow and continuous process. Our ci...

Embodiment 3

[0067] The input port generally has three connection states, that is, the input port is suspended, the input port is pulled to the power supply or ground by an external resistor, and the input port is driven by an external circuit.

[0068] Assuming that the input port is floating, when the power supply voltage is applied to this circuit, the power supply rise curve is unknown, and if it is powered by multiple power supplies, the timing of the power supply is also random, these factors lead to the instantaneous rise of the power supply In the state process, the charge accumulation process on the capacitor Cp is unpredictable, which directly causes the voltage on Cp to be random.

[0069] In most cases, this voltage cannot reach the upper threshold voltage of the Schmitt trigger. Among them, the specific threshold voltage and hysteresis interval are closely related to the specific implementation of the circuit. The selection of circuit parameters can determine the hysteresis ch...

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PUM

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Abstract

The invention provides an input interface circuit. The input end of the input interface circuit is grounded through a stray capacitor, and is connected with a drain electrode of a first MOS tube through a first resistor; a source electrode of the first MOS tube is grounded or connected with a power supply; a grid electrode of the first MOS tube is connected with the output end of the input interface circuit through a second phase inverter; the input end of the input interface circuit is also connected with the output end of the input interface circuit through a second resistor, a first phase inverter and the second phase inverter sequentially. The input interface circuit receives an input signal through the first resistor and the second resistor, the signal passes through the second resistor and is sent to the first phase inverter for phase inversion, and the phase-inverted signal is sent to the input end of the second phase inverter for phase inversion once more, so that the polarity of an output signal is the same as that of the input signal; the input interface circuit starts from the input end of the second phase inverter and feeds back to the grid electrode of the first transistor, and the source electrode of the first transistor is connected with the input end of the input interface circuit through the first resistor so as to form a large positive feedback loop; the positive feedback loop achieves input port characteristics of self bias and zero power consumption.

Description

technical field [0001] This application relates to the technical field of CMOS integrated circuit design, in particular to an input interface integrated circuit and its input interface circuit. Background technique [0002] In the integrated circuit, the external signal of the digital mode is composed of high level and low level, and the intermediate level is used as the transition of high and low levels, which does not contain any meaningful information. Such signals need to enter the integrated circuit through the digital input port. the interior of the circuit. When the core circuit of the integrated circuit is powered on, each external input of the core circuit requires a clear level positioning, otherwise the input is not the fixed level required by the digital signal, but may be between high and low levels any value. For CMOS logic gates, when the input signal is in an indeterminate state, the N-type and P-type transistors in the logic gate will be turned on at the s...

Claims

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Application Information

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IPC IPC(8): H03K19/0175
Inventor 雷王蕾张建敏江群英
Owner XIAMEN FLOWCHIP ELECTRONICS TECH CO LTD
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