Layout design of MOSFET with multiple interdigital grid electrode structures

Abstract

The invention provides a layout deign of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) with multiple interdigital grid electrode structures. The MOSFET comprises a semiconductor substrate, a first interdigital grid electrode structure, a second interdigital grid electrode structure, a body contact zone, a source zone and a drain zone; and the body contact zone is shared by the first interdigital grid electrode structure and the second interdigital grid electrode structure. The body contact zone is shared, so that the utilization rate of the body contact zone can be improved and the parasitic capacitance can be reduced. Compared with an ordinary body contact device, the active zone has high utilization rate; under the same total grid width condition, the area of the body contact zone is reduced by half and the integration level is improved. The middle body zone is shared by the active zones at two sides, so that the occupied area of metal connecting wires is reduced and the parasitic capacitance can be reduced. The parallel connection of grid electrodes at two sides is realized without increasing wiring difficulty and the resistance of the grid electrodes is reduced. The parallel connection of the drain electrodes at two sides is realized without increasing wiring difficulty and the resistance of the drain electrodes is reduced. The design method of the layout structure of devices has a certain application value in the radio frequency circuit field.

Description

technical field [0001] The invention relates to the technical field of semiconductor devices, in particular to a layout design of a MOSFET with a multi-finger gate structure. Background technique [0002] With the continuous development of semiconductor technology, metal-oxide-semiconductor field-effect transistors (MOSFETs) are widely used in integrated circuit design. Silicon-on-insulator technology (SOI), due to the buried oxide layer, has low parasitic capacitance, and the direct frequency of the device is higher than that of bulk silicon technology. Moreover, SOI technology realizes full dielectric isolation of a single device, eliminating the latch-up effect, and Low leakage current, very suitable for low power consumption, high performance applications. With the application of high-resistance substrates, it is possible to integrate high-quality integrated inductors on insulating silicon substrates, and the integration level is higher. At the same time, because of its...

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Problems solved by technology

However, the body contact technology introduces additional parasitic parameters, such as the influence of parasitic resistance and parasitic capacitance, which will affect the RF performance of the device, especially the oscillation frequency reduces the cut-off frequency and oscillation frequency of the device. How to improve the frequency characteristics of the device has always been The focus of research on device work

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