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Method for improving the narrow width effect of shallow trench isolation structure

A shallow trench isolation and narrow width effect technology, which is applied in the field of improving the narrow width effect of shallow trench isolation structures, can solve problems such as lowering of threshold voltage and affecting the performance of semiconductor devices, so as to reduce the update frequency, increase the isolation effect, and improve the process quality. Simple Effects of Process Approach

Inactive Publication Date: 2015-03-18
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology

[0012] The invention provides a method for improving the narrow width effect of the shallow trench isolation structure to solve the problem that the threshold voltage of the semiconductor device decreases with the narrowing of the channel width in the prior art as the size of the semiconductor device shrinks, thereby affecting Problems with the performance of semiconductor devices

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  • Method for improving the narrow width effect of shallow trench isolation structure
  • Method for improving the narrow width effect of shallow trench isolation structure
  • Method for improving the narrow width effect of shallow trench isolation structure

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Embodiment Construction

[0041] The method for improving the narrow-width effect of the shallow trench isolation structure proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will be more clear. It should be noted that the accompanying drawings are all in a very simplified form and use inaccurate ratios, which are only used for convenience and clarity to assist in explaining the present invention. Purpose of the example.

[0042] The core idea of ​​the present invention is: the semiconductor substrate contains a first material layer and a second material layer, and by performing a second etching on the second material layer at the bottom, while ensuring that the effective area of ​​the source / drain region remains unchanged Next, the width of the bottom of the shallow trench isolation structure is enlarged...

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Abstract

The invention provides a method for improving the narrow width effect of a shallow trench isolation structure. The method comprises the steps of providing a semiconductor substrate including a first material layer and a second material layer, sequentially forming an oxide layer and a nitride layer, carrying out etching for the first time to form a first shallow trench isolation groove in the nitride layer, the oxide layer, the first material layer and the second material layer, etching the second material layer for the second time in the first shallow trench isolation groove to form a second shallow trench isolation groove, filling the second shallow trench isolation groove with isolation material, and removing the nitride layer to form a shallow trench isolation structure. By etching the second material layer for the second time, on the premise of ensuring that the effective area of a source / drain region remains unchanged, the bottom width of the shallow trench isolation structure is increased, the isolation effect of the shallow trench isolation structure is improved, the threshold voltage of semiconductor devices is improved to a certain extent, and thus the performance of semiconductor devices is enhanced.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a method for improving the narrow width effect of a shallow trench isolation structure. Background technique [0002] Isolation between components of semiconductor devices is usually achieved by local oxidation of silicon (LOCOS) and shallow trench isolation (Shallow Trench Isolation, STI). [0003] Of the two, the LOCOS method is simple in operation, and can simultaneously form a wide isolation film and a narrow isolation film. However, in the LOCOS method, edge oxidation forms a bird break, which widens the isolation region and reduces the effective area of ​​the source / drain region. Also, in the LOCOS method, stress depending on the difference between thermal expansion coefficients is concentrated to the edge of the oxide film during the formation of the domain oxide film, resulting in the formation of crystal defects on the silicon substrate to cause a large a...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L21/306H01L21/311
CPCH01L21/76224H01L21/30608H01L21/3065
Inventor 赵猛洪中山
Owner SEMICON MFG INT (SHANGHAI) CORP
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