Superjunction device and manufacturing method

A super junction and device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as device recovery current change, device failure, diode hard reverse recovery characteristics, etc.

Active Publication Date: 2017-06-06
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the super junction process, due to the use of alternating P / N thin layers, the body diode of the super junction device, that is, the diode formed between the P-type semiconductor thin layer and the N-type semiconductor thin layer, can operate at a lower voltage such as 50 volts Vds The P-type semiconductor thin layer and the N-type semiconductor thin layer will be completely depleted, which makes the diode have a very hard reverse recovery characteristic. This hard reverse recovery characteristic causes the recovery current of the device to change sharply, resulting in Very high voltage overshoot can cause device failure
At the same time, due to the sharp change of current and voltage, that is, high di / dt and dv / dt will cause electromagnetic interference (EMI-ELEACTROMAGENETIC INTERFERENCE) in the circuit, which will affect the system and even exceed the EMI standard. In this regard, super junction The device is not as good as the conventional MOSFET device, because the depletion of the N-drift region of the conventional MOSFET device always expands with the increase of the voltage (Vds), and the reverse recovery characteristic is soft

Method used

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Embodiment Construction

[0054] Such as figure 1 Shown is the top view of the existing super junction device Figure one . In the top view, the embodiment of the present invention can be divided into zone 1, zone 2, and zone 3. Region 1 is the middle region of the super junction device, which is the current flow region. The current flow region includes alternately arranged P-type regions 25 and N-type regions. The P-type region 25 is also the P-type region formed in the current flow region. The N-type thin layer, the N-type region is also the N-type thin layer formed in the current flow region; in the current flow region, the current will pass through the N-type region from the source to the drain through the channel, and the The P-type region 25 and the N-type region form a depletion region to withstand voltage in the reverse blocking state. Zone 2 and Zone 3 are the terminal protection structure area of ​​the super junction device. When the device is turned on, the terminal protection structure does...

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Abstract

The invention discloses a super-junction device. A current flow region comprises a plurality of N-type thin layers and P-type thin layers which are arranged alternatively. The N-type thin layers comprise two types, and both the two types of N-type thin layers comprise a high-resistance part in the middle and low-resistance parts at the two sides. The charge of the first type of N-type thin layers and that of the P-type thin layers are in balance. The second type of N-type thin layers has a wider high-resistance part, and the charge of the second type of N-type thin layers and that of the P-type thin layers are not in balance. After the P-type thin layers horizontally deplete the second type of N-type thin layers, a P well on the top of the N-type thin layers vertically depletes the high-resistance parts of the second type of N-type thin layers in a gradually expanding way with the increase of reverse bias voltage. The invention further discloses a method for manufacturing the super-junction device. The reverse recovery characteristic of the device can be improved, and the conduction resistance is low.

Description

Technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of a super junction device. Background technique [0002] Super junction MOSFET adopts a new withstand voltage layer structure, using a series of alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers to combine the P-type semiconductor thin layers and N-type semiconductor thin layers at a lower voltage in the off state. Type semiconductor thin layer is depleted to achieve mutual compensation of charges, so that P-type semiconductor thin layer and N-type semiconductor thin layer can achieve high breakdown voltage under high doping concentration, thereby achieving low on-resistance and high breakdown at the same time Voltage, breaking the theoretical limit of traditional power MOSFET. In the US patent US5216275, the above alternately arranged P...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L29/06H01L21/336
CPCH01L29/0634H01L29/66477H01L29/78
Inventor 肖胜安
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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