Superjunction device and manufacturing method thereof

Abstract

The invention discloses a superjunction device. A current flowing area comprises a plurality of N type thin layers and P type thin layers, the N type thin layers and the P type thin layers are alternately arranged, a plurality of grooves are formed in a silicon substrate, and each N type thin layer comprises a first N type thin layer and a second N type thin layer; each first N type thin layer comprises a silicon substrate bottom thin layer between adjacent grooves, each second N type thin layer has lower electrical resistivity, electric charges of at least the second N type thin layers and the adjacent P type thin layers are balanced, electric charges of at least part of N type thin layers and the adjacent P type thin layers are not balanced, and N type areas comprising back ion injection areas are formed at bottoms of the N type thin layers and P type thin layers. The invention further discloses a manufacturing method of the superjunction device. According to the superjunction device and the manufacturing method of the superjunction device, the manufacturing cost can be minimized, and meanwhile, specific on-state resistance of the device and softness coefficient of reverse recovery of the device in a turn-off process can be optimized.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a super junction device; the invention also relates to a manufacturing method of the super junction device. Background technique [0002] The super junction MOSFET adopts a new voltage-resistant layer structure, and uses a series of alternately arranged P-type semiconductor thin layers and N-type semiconductor thin layers to combine the P-type semiconductor thin layers and N-type semiconductor thin layers at a lower voltage in the off state. The thin layer of semiconductor is depleted to achieve mutual compensation of charges, so that the thin layer of P-type semiconductor and thin layer of N-type semiconductor can achieve high breakdown voltage under high doping concentration, so as to obtain low on-resistance and high breakdown at the same time voltage, breaking the theoretical limit of traditional power MOSFETs. In U.S. Patent US5216275, the above...

AI Technical Summary

Problems solved by technology

[0004] In the super junction process, due to the use of alternate P / N thin layers, the body diode of the super junction device, that is, the diode formed between the P-type semiconductor thin layer and the N-type semiconductor thin layer, can operate at a lower reverse bias voltage such as 50 Vds will completely deplete the P-type semiconductor thin layer and the N-type semiconductor thin layer, which makes the diode have a very hard reverse recovery characteristic. This hard reverse recovery characteristic causes the recovery current of the device to change sharply. Severe fluctuations in reverse recovery cause electromagnetic noise (EMI NOISE) in the circuit, which affects the work of other devices in the circuit. In this regard, super junction devices are not as good as conventional MOSFET devices, because conventional MOSFET devices The depletion of the N-drift region always expands with the increase of the voltage (Vds), and the reverse recovery characteristic is soft

[0005] In terms of process selection, multiple epitaxial growth and lithography and implantation processes have complex, long manufacturing cycle and high cost problems. In the trench filling process, it is necessary to deposit on a highly doped substrate before the trench process. The epitaxial layer with a thickness of tens of microns also increases the cost of the process

Images