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A ldpc error correction coding method based on flash memory error interval

An error correction coding and error technology, which is applied in the field of LDPC error correction coding based on the error interval of flash memory, achieves the effect of improving error correction ability and algorithm execution efficiency, improving error correction ability, and overcoming error accompanying information propagation

Active Publication Date: 2016-04-20
HUNAN UNIV
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Problems solved by technology

[0015] The technical problem to be solved by the present invention is to provide a LDPC error correction coding method based on the flash memory error interval to solve the high delay problem of simply using soft decoding in a high-speed storage system and eliminate the Bit-Flipping method for the deficiencies of the prior art Propagation of error codewords during hard decoding improves error correction capability and algorithm execution efficiency

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  • A ldpc error correction coding method based on flash memory error interval
  • A ldpc error correction coding method based on flash memory error interval
  • A ldpc error correction coding method based on flash memory error interval

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Embodiment Construction

[0037] The method of the present invention is divided into the following three steps: the first step is to calculate the key factor q according to the current error rate of the solid-state hard disk channel, thereby obtaining an accurate and specific error interval; the second step is to use the error interval to locate possible error information bits ; The third step is to flip the located information bits according to the combined algorithm rules.

[0038] The specific implementation process is as follows:

[0039] Preparatory steps: Pass the k bits of the original information through the generator matrix G to generate an n-bit codeword containing m-bit redundant information, and store it in the flash memory, where n=m+k satisfies the relationship h mn It is a check matrix, which is used to check whether the read information is correct, and the matrix G is generated kn is a matrix containing only 0 or 1 elements, which is used to add redundant information to the original ...

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Abstract

The invention discloses an LDPC error correction encoding method based on a flash memory error section. The LDPC error correction encoding method comprises the following steps: calculating an accurate error section according to a present error rate of a solid hard disc channel; positioning a possible error position by virtue of the error section; turning over a bit which is already positioned as an error position according to the decoding principle of a Bit-Flipping method. By adopting the LDPC error correction encoding method, the problem of high latency caused by the fact that only soft decoding is used in a high-speed memory system is solved, the spreading of error code words in the hard decoding process of the Bit-Flipping method is eliminated, and the error correction property and the algorithm execution efficiency are improved.

Description

technical field [0001] The invention relates to the field of LPDC error correction coding for NAND flash memory systems, in particular to an LDPC error correction coding method based on flash memory error intervals. Background technique [0002] With the rapid development of the Internet and information systems in various fields of society, the explosive growth of data makes large-capacity storage systems face huge challenges in terms of reliability and performance. The Solid-State Drive (SSD) with NAND Flash as the storage medium has the characteristics of high performance and low power consumption. Development opportunities, the use of Flash media to build a high-fault tolerance, high-efficiency large-capacity solid-state storage system is one of the main development trends of storage systems. Although researchers have carried out various researches on solid-state disks and achieved a series of achievements, the error correction coding technology of solid-state disks is s...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/42
Inventor 胡玉鹏宋顺周超卿敏龙廖优
Owner HUNAN UNIV
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