PMOS structure with SiGe source and drain area and manufacturing method thereof

Abstract

The invention discloses a PMOS structure with a SiGe source and drain area. A first main layer with the Ge concentration gradually increased and a second main layer with the Ge concentration gradually reduced are arranged in a SiGe main layer, the change of gradient of the Ge concentration is formed so that dislocation and stress release caused by the sudden change of the Ge concentration at the interface position of the main layer and a buffering layer can be avoided, the low Ge concentration is restored at the interface position of the main layer and a cap layer and serves as the growth end concentration, and therefore it is ensured that the cap layer well wraps the main layer. The highest position of Ge concentration is the interface layer of the first main layer and the second main layer or the middle layer position in the middle and used for improving the stress of a channel, and therefore the yield of devices is increased, and the performance of the devices is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuit manufacturing technology, in particular to a PMOS structure with SiGe source and drain regions and a manufacturing method thereof. Background technique [0002] With the development of semiconductor integrated circuits, the size reduction of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) has continuously improved the speed, performance, density and functional unit cost of integrated circuits. After entering the 90nm technology era, with the substantial reduction in the size of integrated circuit devices, the junction depth of the source / drain (elevated source / drain) is getting shallower and shallower, and it is necessary to use selective epitaxy technology (selective epi SiGe, abbreviated as SEG) to increase Thick source / drain, where the Si capping layer can protect SiGe, and serve as a sacrificial layer for subsequent silicide reactions, thereby reducing serie...

AI Technical Summary

Problems solved by technology

[0006] However, in the epitaxial process of SiGe with high Ge concentration, due to the sudden change of Ge concentration at the interface between the SiGe buffer layer and the SiGe main layer, and between the SiGe main layer and the Si cap layer, defects such as dislocations will be generated at the interface. like Figure 4 shown

Dislocations will cause stress relaxation, resulting in reduced channel stress and poor device performance

On the other hand, the surface of the bulk layer with high Ge concentration cannot be well covered by the Si capping layer, resulting in exposed SiGe, such as Figure 5 As shown, it is difficult to grow the subsequent NiSi, which leads to the deterioration of the contact performance of the device and the decrease of the device yield.

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