Self-Aligned Contact Hole Etching Method

Abstract

The invention discloses a self-aligned contact hole etching method, which includes the steps of: providing a silicon substrate formed with multiple gate structures; depositing silicon nitride sidewalls; using HDPCVD technology to deposit a first layer including a bud-like structure. layer of phosphosilicate glass; the first layer of phosphosilicate glass is etched, and the etching area is customized by the minimum spacing between adjacent bud-like structures; the etched pattern of the first layer of phosphosilicate glass is used as a mask Etch the silicon nitride sidewalls; remove all the first layer of phosphosilicate glass and form L-shaped gate sidewalls; form a self-aligned source and drain region; nitride the hard mask layer at the gate contact area window The silicon sidewalls are all removed; a second layer of phosphosilicate glass is deposited and planarized; a third layer of undoped silicon dioxide is formed; a photolithography process is used to define a self-aligned contact hole pattern and etching to form a self-aligned contact hole. The invention can reduce the height of the gate structure, increase the gate spacing, reduce the difficulty of PSG filling between the gate structures, enhance the etching ability of the self-aligned contact hole, and improve the etching quality of the self-aligned contact hole.

Description

Technical field [0001] The present invention relates to a semiconductor integrated circuit manufacturing process, and in particular to a self-aligned contact hole etching method. Background technology [0002] like Figure 1 Shown is a cross-sectional view of the self-aligned contact hole structure formed by the existing self-aligned contact hole etching method; the existing self-aligned contact hole etching method includes the following process steps: [0003] Step 1. Provide a silicon substrate 101 formed with multiple gate structures. The gate structure includes a gate dielectric layer 102, a gate polysilicon 103 and a hard mask layer 106 sequentially formed on the surface of the silicon substrate 101. , the pattern of the gate structure is defined by the hard mask layer 106; self-aligned lightly doped drain regions 104 are formed in the silicon substrate 101 on both sides of each gate structure. The gate dielectric layer 102 can be a gate oxide layer, and the gate polys...

AI Technical Summary

Problems solved by technology

[0009] In the existing method, when the self-aligned contact hole 109 on the source-drain region 105 is formed by etching, the self-aligned contact hole 109 will bridge a certain distance d on the silicon nitride sidewall 107, so that the self-aligned contact hole 109 will be formed during etching. The contact hole 109 will cause some damage to the silicon nitride sidewall 107

In addition, when the gate sidewall is formed by the existing method, the thickness of the silicon nitride sidewall 107 on the sidewall of the gate structure will also have a certain loss, and the thickness a of the bottom of the silicon nitride sidewall 107 will always be greater than that of the top. Thickness b

In order to maintain the top thickness b of the silicon nitride spacer 107, the existing method is to increase the thickness of the hard mask layer 106. The increase in the thickness of the hard mask layer 106 will increase the thickness of the entire gate structure. When the gate When the pole spacing c is small, the trench structure between the gate structures will have a larger aspect ratio, which will make it difficult to fill the trench structure between the gate structures during PSG deposition in the subsequent step 4, increasing the Process difficulty; in addition, when the gate spacing c is small, the subsequent self-aligned contact hole etching window will be too small, and the contact hole is not easy to be completely opened to form defects

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