A bionic clock circuit with anti-interference characteristics and its realization method
A clock circuit and circuit technology, applied in the direction of electric pulse generator circuit, etc., can solve the problem that the clock circuit is difficult to resist the interference of complex electromagnetic environment, and achieve the effect of reducing skew, improving stability, and maintaining stable operation.
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Embodiment 1
[0048] Embodiment 1, a bionic clock circuit with anti-disturbance characteristics and its implementation method.
[0049] The neuron circuit unit in this embodiment is a kind of integral and distribution neuron circuit unit, and its structural diagram is as follows figure 2 shown. The neuron circuit unit includes an input terminal 21, an inverter 22, a first switch 23, a second switch 24, a membrane capacitance (C m ) 25, comparison circuit 26, delay circuit 27 and output terminal 28.
[0050] The input terminal 21 is connected to the first switch 23, and the input terminal 21 is used to receive the signal input from the outside, and the signal received by the input terminal 21 is used as the input signal of the corresponding neuron circuit unit.
[0051] The first switch 23 is respectively connected to the input terminal 21 , the inverter 22 and the film capacitor 25 . The signal output by the inverter 22 is used to control the first switch 23 to be closed (or called cond...
Embodiment 2
[0070] Embodiment 2, a bionic clock circuit with anti-disturbance characteristics and its simulation verification.
[0071] Such as Figure 6 As shown, the figure shows 20 nodes, each node represents a CMOS integral distribution neuron circuit unit, and the number of the node (1~20) is the number of the neuron circuit unit. The connection between the neuron circuit units is a synaptic circuit, and the synaptic circuit is a resistor. The connection between neuron circuit units adopts Figure 5 Ring-coupled connection shown.
[0072] The specific structure of each CMOS integral distribution neuron circuit unit is as follows: Figure 7 as shown, Figure 7 , the inverter inv 1 ~inv 12 Essential effect is equal to in embodiment 1 (see figure 2 ) comparison circuit 26 and delay circuit 27; the inverter 22 in Embodiment 1 is not provided in this embodiment, and the PMOS transistor P in this embodiment l Identical to the first switch 23 in Embodiment 1, the NMOS transistor N ...
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