Rapid reliability evaluation method for SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array)

Abstract

The invention specifically provides a rapid reliability evaluation method for an SRAM (Static Random Access Memory) type FPGA (Field Programmable Gate Array). The method comprises the following steps: (1) dividing a to-be-processed VHD (Virtual Hard Disk) source program into L modules according to a module division criterion determined according to a VHDL (Very High Speed Integrated Circuit Hardware Description Language) hardware language; (2) performing integration, mapping, layout wiring and XDL (Xilinx Design Language) file generation operation on the L modules in combination with a hardware design tool ISE (Integrated Software Environment) in sequence; (3) performing rough calculation by using a probability analysis method to obtain the soft error rate of each module and adding the soft error rates to a rough calculation set C1; (4) selecting a threshold value delta for the C1 by using a maximum between-class variance algorithm OSTU; adding the module with the soft error rate of being greater than the delta into an accurate calculation set C2; (5) performing accurate calculation on the soft error rate SER for each module in the accurate calculation set C2 by using a monte carlo method respectively, and saving the results in a protection set S from big to small. While the calculation accuracy is guaranteed, the calculation time in the reliability evaluation process of the SRAM type FPGA can be reduced as much as possible.

Description

Technical field [0001] The invention belongs to the technical field of circuit reliability evaluation, and particularly relates to a reliability evaluation method of an SRAM type FPGA, in particular to a rapid reliability evaluation method for an SRAM type FPGA. Background technique [0002] SRAM FPGA is the mainstream FPGA circuit structure on the market, and it is widely used in aerospace, medical, automotive and other fields. However, SRAM-type FPGAs are prone to soft errors under the bombardment of high-energy particles. Soft errors are mainly manifested as: FPGA circuit configuration bits, that is, SRAM cells change, causing circuit topology logic errors; FPGA flip-flops store logic values ​​change , Resulting in an incorrect circuit operating state. With the continuous advancement of chip manufacturing processes, chip feature sizes are getting smaller and smaller, and the high-energy particle bombardment energy required for soft errors in FPGAs is also reduced, resulting i...

AI Technical Summary

Problems solved by technology

[0012] It can be seen that the Monte Carlo method has the advantage of high calculation accuracy, but its calculation time is long, while the probability analysis method has the advantage of short calculation time, but its calculation accuracy is insufficient

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