Implementation method for assembly lines low in power consumption
An implementation method and pipeline technology, applied in machine execution devices, concurrent instruction execution, etc., can solve problems such as high register inversion rate, reduced dynamic power consumption, and huge data volume, so as to reduce design complexity and dynamic power consumption , The effect of simplifying the circuit structure
Active Publication Date: 2015-06-10
SHANDONG INSPUR SCI RES INST CO LTD
View PDF3 Cites 2 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
[0005] The present invention is aimed at the efficient scheduling of pipelines. For large-scale high-speed protocol processors, the amount of data is huge, and the inversion rate of registers is very high when using conventional methods, which increases design requirements and design difficulties, and the traditional pipeline structure processing method cannot meet the requirements. Existing requirements lead to great risks in circuit back-end design, which is not conducive to circuit designers to design circuits and other deficiencies and defects. A low-power pipeline implementation method is provided, which helps to maintain the scale of registers and logic circuits. In the case of changes, the inversion rate of the register is reduced, which is of great help to the reduction of dynamic power consumption when the circuit continues to work effectively for a long time
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0021] Referring to the accompanying drawings, a brief description will be given below of the implementation of the content of the present invention.
[0022] see figure 1 , which is the traditional pipeline working mode. After the data enters the pipeline for processing, each stage from pipeline 1 to pipeline n has a certain logic algorithm processing operation. This operation is completed within one clock time, and then the processing result data is locked. It is stored in the register and output to the next stage of the pipeline for processing at the next clock. Since the data processed by each stage is almost completely independent in each clock, the data latched into the registers of each stage is almost all updated, and the registers almost need to be completely flipped. This is true for each stage of pipeline processing, so all the registers in the pipeline are almost completely inverted at each clock, and the dynamic power consumption is basically the sum of the nomin...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
The invention discloses an implementation method for assembly lines low in power consumption, and belongs to the field of design of chip assembly lines. The implementation method specifically includes that 1), the novel assembly lines, which are internally provided with register data pointers and externally provided with register stacks, are created; 2), an assembly line master control unit is created in each level of assembly line; 3), data pointer management units are arranged on the register stacks, data flow into the assembly lines, a register of each assembly line is occupied, data corresponding to the register data pointers corresponding to the register stacks are invalid after output of the last level of assembly line, pointers and the corresponding stacks are provided for data recently entering the assembly lines, each level of assembly line updates data corrected by itself to the corresponding register stack, and the master control unit of each level of assembly line determines data outputted to the next level of assembly line according to processing of its level and sends the register data pointer to the corresponding register stack and the next level of master control unit. By the implementation method, overturn ratio of the registers is reduced, and reduction of dynamic power consumption is benefited obviously.
Description
technical field [0001] The invention discloses a method for realizing a low-power consumption assembly line, which belongs to the field of chip design. Background technique [0002] The invention relates to the field of chip design, in particular to a novel implementation method for pipeline scheduling processing of data paths in the circuit implementation process of a network control protocol chip in a multi-node network. [0003] With the continuous development of the server application field, the application requirements of high-end servers have entered an important stage. The realization of complex architecture supports high-end server systems to achieve high-performance indicators, that is, high security, high availability, and high reliability. Among them, the network control chip controls the multi-processor system, so that the internal message transmission of the system can achieve the purpose of high efficiency, reliability, safety and stability. For the design of...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More IPC IPC(8): G06F9/38
Inventor 赵元童元满李仁刚
Owner SHANDONG INSPUR SCI RES INST CO LTD