Shift register, gate drive circuit unit, gate drive circuit and display
A gate drive circuit, shift register technology, applied in static memory, static indicator, digital memory information and other directions, can solve the problem of unfavorable display panels, large area occupied by gate drive circuits, and decreased yield of gate drive circuits and other problems, to achieve the effect of reducing the number, improving the circuit yield, and reducing the cost of the circuit
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Example Embodiment
[0050] Example one:
[0051] Please refer to figure 2 , The shift register in this embodiment includes a signal input module 1, a signal output module 2, a pull-up module 3, and a reset module 4.
[0052] Signal input module 1 is used to receive external start signal V IN And the first clock signal V1, and turn on the signal output module 2; the first input terminal of the signal output module 2 and the output terminal of the signal input module 1 are coupled to the first node Q, and the second input terminal of the signal output module 2 is used for To receive the external second clock signal V2, the output terminal of the signal output module 2 is used to output the scan signal V after the module is turned on OUT One end of the pull-up module 3 is coupled to the first node Q, and the other end is coupled to the output terminal of the signal output module 2. The pull-up module 3 is used to increase the voltage of the first node Q; the reset module 4 is used to connect the first...
Example Embodiment
[0058] Embodiment two:
[0059] Please refer to image 3 , The gate drive circuit unit of this embodiment includes a pull-down module and multiple cascaded shift registers, multiple shift registers share the pull-down module, the pull-down module is used to pull the scan signal output by the signal output module to a low level . The clock signals of the multiple shift registers must have the same cycle and duty cycle, and there is an overlap in the time domain between the clock signals of the adjacent shift registers. The more cascaded shift register stages, the smaller the average number of transistors required for each shift register. However, if there are too many cascaded stages in practical applications, it should be at the upper stage of the low-level maintenance state. The voltage of the first node will be in a floating state due to the excessive number of stages causing the voltage of the second node to remain at a high level, which may cause abnormal output. The gate d...
Example Embodiment
[0079] Example three
[0080] Please refer to Image 6 , The gate drive circuit unit in this embodiment includes 4-stage cascade shift registers (the first stage shift register 31, the second stage shift register 32, the third stage shift register 33, and the fourth stage shift register The connection mode of each part of the register 34) and the first pull-down circuit 41 and the second pull-down circuit 42 is the same as that of the second embodiment, and will not be repeated here. The difference between this embodiment and the second embodiment is that each stage of the shift register does not include the first capacitor. Since in the low-level maintenance phase, the voltage jump amplitude on the first node is related to the voltage division of the gate-drain parasitic capacitance of the first capacitor and the third transistor, the existence of the first capacitor can further increase the clock feedthrough effect of the circuit. Suppression. But when the third transistor ha...
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