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Shift register, gate drive circuit unit, gate drive circuit and display

A gate drive circuit, shift register technology, applied in static memory, static indicator, digital memory information and other directions, can solve the problem of unfavorable display panels, large area occupied by gate drive circuits, and decreased yield of gate drive circuits and other problems, to achieve the effect of reducing the number, improving the circuit yield, and reducing the cost of the circuit

Active Publication Date: 2015-06-10
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The above-mentioned shift register uses a large number of transistors, resulting in a large area occupied by the gate drive circuit, which is not conducive to making a display panel with a narrow frame; at the same time, too many transistors will easily lead to a decrease in the yield of the gate drive circuit

Method used

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  • Shift register, gate drive circuit unit, gate drive circuit and display
  • Shift register, gate drive circuit unit, gate drive circuit and display
  • Shift register, gate drive circuit unit, gate drive circuit and display

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0051] Please refer to figure 2 , the shift register in this embodiment includes a signal input module 1 , a signal output module 2 , a pull-up module 3 and a reset module 4 .

[0052] Signal input module 1 is used to receive the external start signal V IN and the first clock signal V1, and the signal output module 2 is turned on; the first input terminal of the signal output module 2 and the output terminal of the signal input module 1 are coupled to the first node Q, and the second input terminal of the signal output module 2 is used To receive the second external clock signal V2, the output terminal of the signal output module 2 is used to output the scan signal V after the module is turned on OUT ; One end of the pull-up module 3 is coupled to the first node Q, and the other end is coupled to the output end of the signal output module 2, the pull-up module 3 is used to increase the voltage of the first node Q; the reset module 4 is used to reset the first node Q The vol...

Embodiment 2

[0059] Please refer to image 3 , the gate drive circuit unit of this embodiment includes a pull-down module and a plurality of cascaded shift registers, the plurality of shift registers share the pull-down module, and the pull-down module is used to pull the scan signal output by the signal output module to a low level . The current-stage clock signals of multiple shift registers must have the same period and equal duty cycle, and there is an overlapping part in the time domain between the current-stage clock signals of adjacent shift registers. The more cascaded shift register stages, the fewer transistors are required on average for each stage of shift register. However, if there are too many cascaded stages in practical applications, the upper stage that should be in a low-level maintenance state will The voltage of the first node will be in a suspended state due to too many stages causing the voltage of the second node to remain at a high level, which may cause abnormal ...

Embodiment 3

[0080] Please refer to Image 6 , the gate drive circuit unit in this embodiment includes 4 stages of cascaded shift registers (the first stage shift register 31, the second stage shift register 32, the third stage shift register 33 and the fourth stage shift register The register 34 ), the first pull-down circuit 41 , and the second pull-down circuit 42 are connected in the same way as in the second embodiment, and will not be repeated here. The difference between this embodiment and the second embodiment is that each stage of shift register does not include the first capacitor. Because in the low-level maintenance phase, the voltage jump amplitude on the first node is related to the voltage division between the first capacitor and the gate-drain parasitic capacitance of the third transistor, the existence of the first capacitor can further improve the clock feedthrough effect of the circuit. suppression. However, when the size of the third transistor is large (the width is...

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Abstract

The invention discloses a shift register, a gate drive circuit unit, a gate drive circuit and a display. The gate drive circuit comprises the gate drive circuit units in multi-level cascade, each gate drive circuit unit comprises shift registers in multi-level cascade, the plurality of shift registers share a pull-down module, and consequently the number of transistors in the circuit is decreased, and circuit yield is increased. The gate drive circuit can be used for driving a display panel; due to reduction of the transistors in the circuit, size of the circuit is reduced, and manufacturing of a narrow-frame display is benefited; in addition, cost is reduced, circuit yield is increased, and display stability is improved.

Description

technical field [0001] The present application relates to the field of displays, in particular to a shift register, a gate drive circuit unit, a gate drive circuit and a display. Background technique [0002] Liquid crystal displays (LCDs) are the most commonly used mainstream displays today. The traditional liquid crystal display uses an external driver chip circuit to drive the thin-film liquid crystal tube on the panel to realize image display. With the continuous development of technology, gate driver on array (GOA) is widely used in LCD panels, which can reduce the number of peripheral ICs and the corresponding number of connecting wires, thereby reducing the cost of the display module. [0003] In the gate drive circuit, its output voltage is in a low-level state for most of the working time, and due to the clock feedthrough effect, the voltage jump on the clock line or data line will cause the output low level to rise. Therefore, a low-level maintenance circuit is r...

Claims

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Application Information

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IPC IPC(8): G09G3/36G09G3/20G11C19/28
Inventor 张盛东李君梅廖聪维胡治晋李文杰
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL
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