Thin film transistor and manufacturing method thereof, array substrate and display device

Abstract

The invention relates to the technical field of semiconductor device preparation, and discloses a thin film transistor, a manufacturing method thereof, an array substrate and a display device. The source electrode and the drain electrode of the thin film transistor are located on the active layer, and the entire active layer is located in the same plane, which overcomes the problem of easy disconnection of the active layer in the prior art due to difficulty in climbing, and the active layer The thickness is uniform, no breakdown and short circuit phenomenon occurs, and the yield rate of the thin film transistor is improved. Furthermore, the source electrode and the drain electrode are arranged in a non-same-layer structure, the distance between the source electrode and the drain electrode can be flexibly adjusted, the narrow channel can be realized more easily, and the performance of the thin film transistor can be improved.

Description

Technical field [0001] The invention relates to the technical field of semiconductor device preparation, in particular to a thin film transistor and a manufacturing method thereof, an array substrate and a display device. Background technique [0002] Combine figure 1 with figure 2 As shown, in a thin film transistor (TFT for short), the source electrode 3, the drain electrode 4 and the gate electrode 1 are all arranged on the same side of the active layer 2. According to the position of the gate electrode 1 relative to the active layer 2, coplanar TFTs are divided into top-gate coplanar TFTs (combined figure 1 Shown) and bottom-gate coplanar TFT (combined figure 2 Shown). [0003] Thin Film Transistor Liquid Crystal Display (TFT-LCD) has the characteristics of small size, low power consumption, no radiation, and relatively low manufacturing cost, and it occupies a dominant position in the current flat panel display market. When coplanar TFT is used in TFT-LCD, for top-gate copl...

AI Technical Summary

Problems solved by technology

When coplanar TFT is used in TFT-LCD, for top gate coplanar TFT, such as figure 1 As shown, the pixel electrode 5 is in electrical contact with the drain electrode 4 through the via hole penetrating the passivation layer 102 and the gate insulating layer 101. Since the depth of the via hole is too large, it is difficult to climb the slope, and the pixel electrode 5 is easily disconnected, causing electrical contact. poor sexual contact

However, if the electrical connection between the pixel electrode 5 and the drain electrode 4 is realized in the form of a jumper, the number of Masks will be increased, and the production cost will be increased.

For the bottom gate coplanar TFT, such as figure 2 As shown, the active layer 2 overlaps the source electrode 3 and the drain electrode 4, and the etching process for forming the source electrode 3 and the drain electrode 4 results in rough sides of the source and drain metal. Since the thickness of the active layer 2 is very thin, when When it is lapped on the source electrode 3 and the drain electrode 4, the sides of the source electrode 3 and the drain electrode 4 are rough and climb, which makes the active layer 2 easy to break, and the thickness is uneven, and it is easy to shock during the power-on process. short circuit

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