Static Random Access Memory (SRAM) unit forming method

Abstract

An SRAM unit forming method comprises forming first, second, third, fourth, fifth and sixth fins; forming a first grid crossing the first, second and third fins and a second grid crossing the first and second fins, wherein the first and second fins between the first and second grids are a first drain; forming a third grid crossing the fourth, fifth and sixth fins and a fourth grid crossing the fifth and sixth fins, wherein the fifth and sixth fins between the third and fourth grids are a second drain; forming a fifth source and a third drain of the third fin on the two sides of the first grid; forming a sixth source and a fourth drain of the fourth fin on the two sides of the third grid; forming an interlayer dielectric layer; performing first graphing to form a first groove crossing the first and second fins of the first drain and the third fin of the third drain; performing second graphing to form a second groove crossing the fifth and sixth fins of the second drain and the fourth fin of the fourth drain; forming a first metal layer in the first groove and a second metal layer in the second groove. By the aid of the method, the SRAM unit is achieved technologically.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for forming an SRAM unit. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] A static random access memory includes a plurality of static random access memory units (hereinafter referred to as SRAM units), the plurality of SRAM units are arranged in an array, and a SRAM unit includes six transistors (6-T). As the integration level of integrated circuits increases, the feature size of SRAM cells gradually decreases and the wafer area occupied by them becomes smaller and smaller. Compared with the size of the planar MOS transistor, the size of the fin field effect transistor is smal...

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Problems solved by technology

[0012] The problem solved by the present invention is that the signal transmission speed of the existing SRAM unit comprising six fin field effect transistors is low and the performance is not good

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