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Digital calibration-based skew cancellation for long-reach mipi d-phy serial links

A serial link and serial communication technology, which is applied in the field of communication link calibration, can solve problems such as large skew, limiting the maximum data rate of link transmission, etc.

Active Publication Date: 2015-07-08
OMNIVISION TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In long-distance applications, the skew can be large enough to limit the maximum data rate transmitted by the link

Method used

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  • Digital calibration-based skew cancellation for long-reach mipi d-phy serial links
  • Digital calibration-based skew cancellation for long-reach mipi d-phy serial links
  • Digital calibration-based skew cancellation for long-reach mipi d-phy serial links

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Detailed description of the invention

[0015] figure 1 A schematic block diagram comprising portions of two circuits, eg, integrated circuits (ICs) connected by a MIPI high-speed serial link. Please refer to figure 1 , a first integrated circuit (IC) 10, which may be referred to as a "master integrated circuit" ("Master IC"), is connected via a MIPI high-speed serial link 14 to, and may communicate with a second integrated circuit (IC) 12 for communication. Such as figure 1 As shown, a reference clock signal is input to a frequency multiplier 16 of a phase locked loop (PLL), which outputs a clock signal at a bit rate. The bit rate clock signal is applied to a pair of D flip-flops 18 and 22 which are triggered on the rising and falling edges of the bit rate clock signal, respectively. Flip-Flop 18 The output is applied to the D input of flip-flop 18 such that flip-flop 18 generates a double data rate (DDR) clock signal and outputs the DDR clock signal at its Q output. T...

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Abstract

A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.

Description

technical field [0001] The present invention relates to the calibration of communication links, and in particular, to the de-skew of MIPI D-PHY serial links. Background technique [0002] In mobile phone technology, the Mobile Industry Processor Interface (MIPI) D-PHY (Physical Layer) serial link is the most prevalent and successful high-speed serial link for mobile phones for chip-to-chip intercom road standard. Conventional MIPI D-PHY links operate at low power, while having shorter range, eg, on printed circuit board (PCB) traces of less than about 30 centimeters. In conventional MIPI D-PHY links, a forward Double Data Rate (DDR) clocking scheme is used for simplified and power efficient receiver design. The transmission of the high-speed DDR clock usually has a quadrature phase relationship with the link data. Typical practical data transfer speed limits today are approximately 1.0 gigabytes per lane (Gbs / lane). [0003] In devices larger than mobile phones, such as ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40G06F13/42
CPCG06F1/10G06F13/40G06F1/08G11C7/1066G11C7/1093G11C29/022G11C29/023G11C29/028G11C2207/2254H04L7/0004H04L7/0008H04L7/0041H04L7/033
Inventor 吴庆乐刘民
Owner OMNIVISION TECH INC
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