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Electrostatic protection circuit

An electrostatic protection and circuit technology, applied in the direction of emergency protection circuit devices, circuits, circuit devices, etc., can solve the problems of unintentional MOS transistors, internal circuit operation failures, and insufficient startup of power supply voltage.

Inactive Publication Date: 2015-08-12
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the time constant is large, when the power is turned on, the trigger circuit responds to a change in the power supply voltage or a fluctuation in the power supply voltage due to the operation of the internal circuit, and there is a possibility that although there is no ESD surge , but the MOS transistors used for discharge may also inadvertently operate
If the MOS transistor used for discharge operates unintentionally when the power supply is turned on, there are cases where the power supply voltage does not start up sufficiently and an operation failure of the internal circuit occurs

Method used

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Examples

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no. 1 example

[0029] figure 1 is a schematic diagram showing the electrostatic protection circuit according to the first embodiment. The electrostatic protection circuit according to the embodiment includes a first trigger circuit 3 connected between the first power terminal 1 and the second power terminal 2 . The trigger signal of the first trigger circuit 3 is supplied to the first buffer circuit 4 . The first buffer circuit 4 amplifies the trigger signal from the first trigger circuit 3 and supplies the amplified trigger signal to the first switch circuit 5 . The conduction of the first switch circuit 5 is controlled by a driving signal from the first buffer circuit 4 .

[0030] The second trigger circuit 6 is connected in parallel with the first trigger circuit 3 between the first power supply terminal 1 and the second power supply terminal 2 . The trigger signal of the second trigger circuit 6 is supplied to the second buffer circuit 7 . The second buffer circuit 7 amplifies the tr...

no. 2 example

[0036] figure 2is a schematic diagram showing an electrostatic protection circuit according to the second embodiment. The same reference numerals and symbols are attached to the constituent elements corresponding to those of the above-described embodiment. In this embodiment, the first trigger circuit 3 includes a series circuit of a resistor 31 and a capacitor 32 . A common node 33 of the resistor 31 and the capacitor 32 is connected to the first buffer circuit 4 . The first buffer circuit 4 includes three stages of inverters 41 , 42 , 43 connected in series. For example, each of the inverters 41, 42, 43 is configured with a CMOS inverter. The first buffer circuit 4 amplifies the trigger signal from the first trigger circuit 3 and supplies the drive signal to the first switch circuit 5 . The first switch circuit 5 includes an NMOS transistor 51 . The drive signal from the first buffer circuit 4 is supplied to the gate electrode of the NMOS transistor 51 . The source el...

no. 3 example

[0046] image 3 is a schematic diagram showing an electrostatic protection circuit according to the third embodiment. The same reference numerals and signs are attached to the constituent elements corresponding to those of the above-described embodiment, and their descriptions are omitted. The present embodiment includes a holding unit 10 that holds the level of the input signal of the second buffer circuit 7 for a predetermined time. The holding unit 10 includes an inverter 101 connected in antiparallel to the inverter 71 of the second buffer circuit 7 . For example, the inverter 101 is configured with a CMOS inverter. A feedback circuit is constituted in which, if the potential at the common node 63 becomes high level, an output signal of low level is supplied from the inverter 71 to the inverter circuit 101, and a signal of high level is supplied from the inverter circuit 101 to the inverter circuit 101. The phaser 101 is supplied to the inverter 71 . The input signal l...

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Abstract

According to one embodiment, an electrostatic protection circuit includes a first trigger circuit that is connected between a first power supply terminal and a second power supply terminal, and a second trigger circuit. The circuit includes a first buffer circuit that outputs a drive signal in response to a trigger signal of the first trigger circuit, and a second buffer circuit that outputs a drive signal in response to a trigger signal of the second trigger circuit. A shunt circuit includes a first switch circuit and a second switch circuit connected in series between the first and second power supply terminals. A conduction of the first switch circuit is controlled by a drive signal of the first buffer circuit, and a conduction of the second switch circuit is controlled by a drive signal of the second buffer circuit.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims the benefit of priority from Japanese Patent Application No. 2014-023440 filed on February 10, 2014, the entire contents of which are incorporated herein by reference. technical field [0003] Embodiments described herein relate generally to electrostatic protection circuits. Background technique [0004] Recently, various proposals have been made for protection circuits regarding electrostatic discharge (ESD). ESD means a discharge from a charged person or machine to a semiconductor device, or from a charged semiconductor to ground potential, etc. With respect to a semiconductor device, if ESD occurs, a large amount of electric charge from terminals of the semiconductor device becomes a current flowing into the semiconductor device. The charges generate a high voltage inside the semiconductor device, thereby causing insulation breakdown of internal elements or failure of the s...

Claims

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Application Information

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IPC IPC(8): H02H9/04
CPCH02H9/044H02H9/046H01L27/0248
Inventor 加藤一洋一岐村岳人
Owner KK TOSHIBA
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