Electrostatic protection circuit
An electrostatic protection and circuit technology, applied in the direction of emergency protection circuit devices, circuits, circuit devices, etc., can solve the problems of unintentional MOS transistors, internal circuit operation failures, and insufficient startup of power supply voltage.
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[0028] (First embodiment)
[0029] figure 1 Is a schematic diagram showing the electrostatic protection circuit according to the first embodiment. The electrostatic protection circuit according to the embodiment includes a first trigger circuit 3 connected between the first power terminal 1 and the second power terminal 2. The trigger signal of the first trigger circuit 3 is provided to the first buffer circuit 4. The first buffer circuit 4 amplifies the trigger signal from the first trigger circuit 3 and provides the amplified trigger signal to the first switch circuit 5. The conduction of the first switch circuit 5 is controlled by a drive signal from the first buffer circuit 4.
[0030] The second trigger circuit 6 and the first trigger circuit 3 are connected in parallel between the first power terminal 1 and the second power terminal 2. The trigger signal of the second trigger circuit 6 is provided to the second buffer circuit 7. The second buffer circuit 7 amplifies the t...
Example
[0035] (Second embodiment)
[0036] figure 2 Is a schematic diagram showing an electrostatic protection circuit according to the second embodiment. The same reference numerals and signs are attached to the construction elements corresponding to the construction elements of the above-described embodiment. In this embodiment, the first trigger circuit 3 includes a series circuit of a resistor 31 and a capacitor 32. The common node 33 of the resistor 31 and the capacitor 32 is connected to the first buffer circuit 4. The first buffer circuit 4 includes three-stage inverters 41, 42, 43 connected in series. For example, each of the inverters 41, 42, 43 is configured with a CMOS inverter. The first buffer circuit 4 amplifies the trigger signal from the first trigger circuit 3 and supplies the driving signal to the first switch circuit 5. The first switch circuit 5 includes an NMOS transistor 51. The drive signal from the first buffer circuit 4 is supplied to the gate electrode of...
Example
[0045] (Third embodiment)
[0046] image 3 Is a schematic diagram showing an electrostatic protection circuit according to the third embodiment. The same reference numerals and signs are attached to the construction elements corresponding to the construction elements of the above-mentioned embodiment, and their descriptions are omitted. This embodiment includes a holding unit 10 that holds the level of the input signal of the second buffer circuit 7 for a predetermined time. The holding unit 10 includes an inverter 101 which is connected in anti-parallel to the inverter 71 of the second buffer circuit 7. For example, the inverter 101 is configured with a CMOS inverter. A feedback circuit is constituted in which, if the potential at the common node 63 becomes a high level, a low-level output signal is supplied from the inverter 71 to the inverter circuit 101, and a high-level signal is reversed from The phaser 101 is provided to the inverter 71. The feedback circuit keeps th...
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