A device for tsv self-detection and classification verification

Abstract

The invention discloses a device used for TSV self detection and classification check. TSVs are connected between an upper chip layer and a lower chip layer; the top ends of the TSVs in the upper chip layer are connected in pairs so as to form a closed ring, and an upper common point O is connected with the top ends of the TSVs respectively, and the upper chip layer is adopted as a receiving end; the upper common point O is connected with a time delay device so as to be adopted a roof of joint rebound of the TSVs; on the lower chip layer, an exclusive-OR gate is connected between the lower end points of every two TSVs, the output ends of the exclusive-OR gates are connected with the triggering ends of respective triggers in a one-to-one correspondence manner, and the output ends of the triggers are connected with a decoder; a lower common point F on the lower chip layer is connected with the lower ends of the TSVs respectively, and the lower chip layer is adopted as a receiving end; the top end of one of the TSVs is connected with the time delay device formed by a buffer and an phase inverter, and the lower end of the TSV is connected with a data comparison device. With the device of the invention adopted, a testing process can be simplified, and testing cost can be reduced, and testing precision can be guaranteed.

Description

technical field [0001] The invention relates to a device for TSV self-detection and classification verification. Background technique [0002] With the continuous development of integrated circuit manufacturing technology, the size of transistors is also shrinking, and very large scale integrated circuit (VLSIC) has been developed rapidly; however, in recent years, according to the report of the International Semiconductor Development Roadmap (ITRS), the process There is a bottleneck in size. In order to continue Moore's Law and promote the advancement of the semiconductor industry, people have proposed the concept of three-dimensional (3D) IC. This technology mainly uses through silicon via (through silicon via, TSV) technology to realize the vertical communication on the interconnection. As a new type of semiconductor product, 3D IC continues Moore's Law. Compared with 2D IC, it has many advantages, but it also brings many challenges. [0003] 3D integrated circuits rea...

AI Technical Summary

Problems solved by technology

As a new type of semiconductor product, 3D IC continues Moore's Law. Compared with 2D IC, it has many advantages, but it also brings many challenges.

[0005] However, the current TSV technology is not yet fully mature. In the TSV preparation process, there are two typical defects: insulating layer short circuit defect and bump open circuit defect.

However, the accuracy of this method is not high enough, the control signal is complicated, and it is difficult to realize

[0015] The third is to add scan chains and scan islands on each layer of chips, and use them to send control signals for comparison before and after transmission to achieve the purpose of testing TSV, but this method has a large area cost

[0016] The fourth is to conduct RC modeling on two TSVs, and use voltage division and charge sharing technology to realize the test before TSV bonding. However, there is noise in the actual circuit, and the theoretical value is used to reflect the actual situation. The accuracy cannot be guaranteed, and the fault coverage rate is low.

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