Formation method of semiconductor structure

Abstract

According to a semiconductor structure fabrication method, a semiconductor substrate having gate structures is provided. Sidewalls of the gate structures may be covered by a spacer layer. An epitaxy process is performed to form a semiconductor epitaxial material layer covering the gate structures, the spacer layer, and the semiconductor substrate. Then, an etching process is performed to form a first semiconductor epitaxial layer on the semiconductor substrate at the two sides of the gate structures. Further, a selective epitaxy process is performed by using a deposition gas and an etching gas, forming a second semiconductor epitaxial layer. The formed second semiconductor epitaxial layer may repair or compensate the first semiconductor epitaxial layer along the horizontal direction. The epitaxy process, the etching process, and the selective epitaxy process are repeated successively to form elevated source / drain regions. The formed elevated source / drain regions may have a flat top surface without any angles.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration in order to achieve higher computing speed, larger data storage capacity, and more functions. Therefore, Therefore, the gate structure of the complementary metal oxide semiconductor (ComplementaryMetalOxideSemiconductor, CMOS) transistor becomes thinner and shorter than before. In order to obtain better electrical performance, it is usually necessary to improve the performance of semiconductor devices by controlling the carrier mobility. A key element of the technology is controlling the stress in the transistor channel. For example, by properly controlling the stress and increasing the mobility of carriers (electrons in n-channel ...

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Problems solved by technology

[0007] However, there are still defects in the raised source / drain regions formed by the prior art

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