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Groove structure of groove-type VDMOS and manufacturing method for groove structure of groove-type VDMOS

A groove type and groove technology, which is applied in the manufacture of semiconductor/solid-state devices, electrical components, circuits, etc., can solve the problems of rising device manufacturing costs, improve the yield, improve the internal shape of the groove, and reduce the process effect of complexity

Inactive Publication Date: 2016-01-06
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to reduce the width of the trench, it is necessary to use more advanced lithography equipment, which greatly increases the cost of device manufacturing

Method used

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  • Groove structure of groove-type VDMOS and manufacturing method for groove structure of groove-type VDMOS
  • Groove structure of groove-type VDMOS and manufacturing method for groove structure of groove-type VDMOS
  • Groove structure of groove-type VDMOS and manufacturing method for groove structure of groove-type VDMOS

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Embodiment 1

[0060] This embodiment is the process of preparing the trench structure of the trench type VDMOS power device by the method of the present invention, as shown in Figure 4 (a) and Figure 4 (b), wherein, Figure 4 (a) is the process of this embodiment Flowchart, Figure 4(b) shows the implementation effect diagram corresponding to the process flow of Figure 4(a), including the following steps:

[0061] S21, growing a silicon oxide layer 12 on the silicon wafer substrate 11;

[0062] In this step, the method for growing the silicon oxide layer 12 is thermal oxidation, including wet oxygen oxidation and dry oxygen oxidation, and the thickness of the silicon oxide layer 12 is 0.1 μm˜10 μm. See S21' for the implementation effect of this step.

[0063] S22, using the photoresist 13 to form a mask pattern on the silicon oxide layer 12 through a photolithography process;

[0064] See S22' for the implementation effect of this step.

[0065] S23, using dry etching to etch the silicon o...

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Abstract

The invention discloses a groove structure of a groove-type VDMOS and a manufacturing method for the groove structure of the groove-type VDMOS. The method comprises steps of forming an oxide layer on a substrate; photoetching the surface of the oxide layer to form groove windows; preparing a layer of nitride on an upper surface of the oxide layer and in the groove windows, wherein the nitride forms first side walls, adhered to the oxide, in the groove windows; preparing a layer of oxide on the nitride, wherein the oxide forms second side walls, adhered to the nitride, in the groove windows; and etching the oxide, the nitride and the substrate in sequence, and saving the first side walls and the second side walls to form grooves. Compared with the prior art, the invention prepares double side walls in the groove windows, reduces the groove width and channel resistance, eliminates limitation on the groove width by the photoetching process capability, and has advantages of reducing the device manufacturing cost, improving device performances and the like.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a trench structure of a trench type VDMOS (vertical double diffused field effect transistor) and a manufacturing method thereof. Background technique [0002] The drain and source poles of the vertical double diffused field effect transistor (VDMOS) are respectively on both sides of the device, so that the current flows vertically inside the device, increasing the current density, improving the rated current, and the on-resistance per unit area is also small, which is a A very versatile power device. At present, the development direction of the vertical double diffused field effect transistor is: 1. Reduce the forward conduction resistance to reduce the static power loss; 2. Increase the switching speed to reduce the transient power loss. [0003] Reducing static power loss is mainly achieved by reducing the total on-resistance of the device. ...

Claims

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Application Information

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IPC IPC(8): H01L29/06H01L21/336
Inventor 李理马万里赵圣哲
Owner PEKING UNIV FOUNDER GRP CO LTD
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