Chip embedded-type encapsulation structure with reinforcing structure and encapsulation method of same

Abstract

The invention discloses a chip embedded-type encapsulation structure with a reinforcing structure and an encapsulation method of the same, which belong to the technical field of semiconductor encapsulation. The chip embedded-type encapsulation structure with the reinforcing structure comprises chip single bodies and a thin film encapsulating body, wherein one or more than one chip single bodies are embedded from the back face into the thin film encapsulating body, the upper surfaces of the chip single bodies and the upper surface of the thin film encapsulating body are covered by an insulated thin film layer I, an opening of the insulated thin film layer I is disposed in the upper surface of a chip electrode, a re-wiring metal layer is formed on the upper surface of the insulated thin film layer, the re-wiring metal layer is respectively electrically connected to the chip electrodes, an input end/output end is disposed on the outmost layer of the re-wiring metal layer, a connecting part is formed at the input end/output end, and the back face of the thin film encapsulating body is equipped with a silicon substrate reinforcing plate. The encapsulation method disclosed by the invention reduces thicknesses of products, increases product reliability and realizes the multi-chip encapsulation structure through wafer-level technological forming.

Description

technical field [0001] The invention relates to a chip embedded packaging structure with a strengthening structure and a packaging method thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] With the development of semiconductor silicon technology, the critical size of the chip is getting smaller and smaller. In order to reduce the cost, the more advanced chip manufacturing process with higher integration level tends to be selected when making the chip, which makes the size of the chip more and more Smaller, the I / O density on the chip surface is getting higher and higher. However, at the same time, the manufacturing process and surface mount technology of printed circuit boards have not been greatly improved. For such a chip with relatively high I / O density, if wafer-level packaging is performed, in order to ensure that the chip to be packaged and the printed circuit board can form an interconnection, the high-density I / O must...

AI Technical Summary

Problems solved by technology

[0003] 1. The existing wafer-level chip fan-out packaging structure requires substrates (1-6) to achieve fan-out, and for small chips with high pin counts, multi-layer substrates (1-6) are required to be fan-out multiple times to be compatible with printing The completion of the interconnection on the circuit board not only increases the mismatch probability of the ever-increasing interconnection pitch and heat dissipation difficulties, but also reduces the reliability of the product, and the existence of the substrate (1-6) makes the thickness of the entire package structure unable to be reduced. The body thickness of the existing wafer-level chip fan-out packaging structure is 700-1500 microns;

[0004] 2. The existing wafer-level chip fan-out packaging structure requires the substrate (1-6) to realize fan-out, which often limits the addition of various chips with different functions, which is not conducive to the integrated development of portable electronic devices

Images