A kind of heterojunction solar cell and its preparation method, surface passivation method
A solar cell and heterojunction technology, applied in circuits, photovoltaic power generation, electrical components, etc., can solve the problems of reducing the open circuit voltage of the battery, deteriorating the passivation quality, reducing the performance of the battery, etc., so as to improve the open circuit voltage and reduce the defect state density. , the effect of improving battery performance
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Embodiment 1
[0038] Embodiment 1: Annealing is performed after the formation of the first intrinsic layer I layer and the second intrinsic layer I layer on both sides of the crystalline silicon wafer, and the formation of the doped layer N layer, specifically:
[0039] Before depositing the first intrinsic layer I layer on the first side surface of the crystalline silicon wafer, the method further includes: depositing a second intrinsic layer I layer on the second side surface of the crystalline silicon wafer; A doped N layer is deposited on the upper surface; wherein the first side surface of the crystalline silicon wafer is opposite to the second side surface. In specific implementation, such as image 3 Shown, including:
[0040] Step 302, the second intrinsic layer I is deposited, that is, hydrogenated amorphous silicon is deposited on the second side surface of the cleaned crystalline silicon wafer to form the second intrinsic layer I;
[0041] Step 304, the doped layer N layer is deposited...
Embodiment 2
[0045] Embodiment 2: Annealing is performed between the formation of the first intrinsic layer I layer and the second intrinsic layer I layer on both sides of the crystalline silicon wafer, specifically:
[0046] After annealing the first intrinsic layer I and before depositing the doped layer P on the surface of the annealed first intrinsic layer I, the method further includes: on the second side surface of the crystalline silicon wafer Depositing a second intrinsic layer I layer; depositing a doped layer N layer on the second intrinsic layer I layer; wherein, the first side surface of the crystalline silicon wafer is opposite to the second side surface. In specific implementation, such as Figure 4 Shown, including:
[0047] Step 402, the first intrinsic layer I is deposited, that is, hydrogenated amorphous silicon is deposited on the first side surface of the cleaned crystalline silicon wafer to form the first intrinsic layer I;
[0048] Step 404, annealing, that is, annealing th...
Embodiment 3
[0052] Embodiment 3: Annealing is performed after the formation of the first intrinsic layer I layer and the second intrinsic layer I layer on both sides of the crystalline silicon wafer, and the formation of the doped layer N layer, specifically:
[0053] After depositing the first intrinsic layer I layer on the first side surface of the crystalline silicon wafer, before annealing the first intrinsic layer I layer, the method further includes: depositing a second intrinsic layer on the second side surface of the crystalline silicon wafer The characteristic layer I layer; the doped layer N layer is deposited on the second intrinsic layer I layer; wherein the first side surface of the crystalline silicon wafer is opposite to the second side surface. In specific implementation, such as Figure 5 Shown, including:
[0054] Step 502, the first intrinsic layer I is deposited, that is, hydrogenated amorphous silicon is deposited on the first side surface of the cleaned crystalline silico...
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