SRAM memory cell, SRAM memory and control method thereof

Abstract

The invention provides an SRAM memory cell, an SRAM memory and a control method thereof. The memory cell comprises a first pull-up transistor and a first parallel pull-down transistor, a first inverter is formed by connecting the first pull-up transistor and the first parallel pull-down transistor together, wherein the first parallel pull-down transistor is formed by connecting a first pull-down transistor and a second pull-down transistor in parallel; a second inverter is formed by connecting the second pull-up transistor and the second parallel pull-down transistor as well as connecting the second pull-up transistor and the second parallel pull-down transistor together, wherein the second parallel pull-down transistor is formed by a third pull-down transistor and a fourth pull-down transistor in parallel; and the first inverter and the second inverter are performed by cross coupling. According to the memory cell, control capability during a production process is enhanced, read-out current and static state noise tolerance of a dual-port SRAM unit can be increased, the mismatch ratio of the memory cell is improved, and the performance and yield rate of the SRAM memory cell can be increased.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an SRAM storage unit, an SRAM memory with the SRAM storage unit and a control method for the SRAM memory. Background technique [0002] With the continuous development of digital integrated circuits, on-chip integrated memory has become an important part of digital systems. Static Random Access Memory (Static Random Access Memory, referred to as SRAM) has become an indispensable and important part of on-chip memory due to its advantages of low power consumption and high speed. SRAM can hold data as long as it is powered, there is no need to constantly refresh it. [0003] Compared with single-port SRAM (Single-portSRAM, SP-SRAM for short) which has only one port for read and write operations, dual-port SRAM (Dual-portSRAM, DP-SRAM for short) has two ports, and each port can perform Read or write operations increase memory bandwidth. Therefore, DP-SRAM is widely use...

AI Technical Summary

Problems solved by technology

[0004] With the continuous shrinking of memory size, the yield of DP-SRAM is facing more challenges, because with the decrease of input voltage (VDD) and the increase of transistor mismatch rate, the write noise margin (WNM) and Read Static Noise Margin (RSNM) gets worse and worse

In addition, due to the continuous shrinking of the device size, the read current Iread is also reduced, making it difficult to avoid the problem of read access failure caused by the defect of the bit line swing.

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