Chemical mechanical polishing (CMP) method

Abstract

The invention discloses a chemical mechanical polishing (CMP) method. The method includes the steps that first flaw distribution of a chip to be processed is obtained according to the thickness of an initial oxide layer, and flaw parameters of a flaw area of the chip to be processed are obtained according to the first flaw distribution; the optimizing thickness of the oxide layer is determined according to the flaw parameters, so that CMP flaws are reduced; second flaw distribution of the chip to be processed in the optimizing thickness is obtained, and dummy fill is carried out on the chip to be processed according to the second flaw distribution; and CMP is carried out on the chip to be processed after dummy fill. By the adoption of the method for carrying out CMP on the chip to be processed, the unevenness of the surface of the chip is relieved, the dummy fill quantity is reduced, and therefore the interconnection line parasitic effect caused by dummy fill is substantially reduced.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to a chemical mechanical grinding method. Background technique [0002] VLSI chips are stacked layer by layer in the manufacturing process. As the integration level becomes higher and higher, the feature size of the chip becomes smaller and smaller, and the flatness of each layer of material in the manufacturing process is raised. higher and higher requirements. The chemical mechanical polishing (CMP) process is a common global planarization method in the chip manufacturing process. Due to the different material properties of media such as metals and oxides, the removal rates of different media during the CMP process are not the same, and the removal rate is different. Different materials need to use different abrasives and different process conditions, so the whole CMP process is divided into three stages: P1 stage (coarse polishing stage), P2 stage (medium polish...

AI Technical Summary

Problems solved by technology

When the P3 stage is over, two problems may arise: metal dishing (Disshing) and oxide layer erosion (Erosion). These two defects are closely related to layout graphic features such as metal line width and line spacing, which affect the flatness of the chip surface. The main factor of degree of

However, the filling of redundant metal brings about an important problem, which is the parasitic effect of interconnection: redundant metal, as a parasitic element of interconnection, can cause RC delay of interconnection and crosstalk of signals, especially in today's Integrated circuits are developing in the direction of high speed, high density, and low power consumption. The parasitic effect of interconnect lines caused by redundant metal has become a key factor restricting the manufacturing of deep submicron integrated circuits.

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