Power-on reset circuit

Abstract

The invention discloses a power-on reset circuit. The circuit comprises a first voltage division circuit connected between a power supply voltage and the ground. A plurality of resistors and one first NMOS tube are serially connected to form the first voltage division circuit. A grid electrode and a drain electrode of the first NMOS tube are serially connected between an output end of the first voltage division circuit and the ground. A source electrode of a second NMOS tube is grounded, a grid electrode is connected with an overturn voltage output by the first voltage division circuit, and a drain electrode is connected with the power supply voltage through a third resistor. The drain electrode of the second NMOS tube outputs a power-on reset signal. The power-on reset signal is reversed by an inverter, and then a reset signal is output. According to the invention, the first NMOS tube is capable of compensating the threshold voltage of the second NMOS tube controlled by the overturn voltage, so that the influences of the threshold voltage of the second NMOS tube on the power-on process when the threshold voltage of the second NMOS tube changes along with PVT are reduced, and the discreteness of the overturn voltage is lowered.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a power-on reset circuit. Background technique [0002] The digital circuit (digital) part in the integrated circuit (IC) chip of the mixed-signal very large-scale integrated circuit (VLSI) will cause the chip to not work normally due to the unsteady state of the power supply during the power-on process. The power-on reset circuit (PowerOnReset, POR) that provides a reset signal, and the trip voltage (Tripvoltage) of the POR circuit is seriously affected by the process PVT. In the field of semiconductor integrated circuit manufacturing, PVT is the process, voltage and temperature conditions that the device meets In general, the process, voltage and temperature all have a certain error range; therefore, because the devices of the circuit are affected by PVT, the performance parameters of the devices will not be exactly the same, such as the threshold voltage of the MOS transis...

AI Technical Summary

Problems solved by technology

[0013] Equation (4) is the V obtained by substituting Equation (1) and Equation (2) into Equation (3) DD with V THN101 It can be seen that the flipping voltage Vtrip of the existing power-on reset circuit will be directly affected by the threshold voltage of the NMOS transistor M101

However, in a semiconductor integrated circuit, the threshold voltage of the NMOS transistor M101 will not remain constant. The same NMOS transistor M101 will change with changes in voltage and temperature, and the threshold voltages of the NMOS transistors formed at different positions on the same wafer will also be different from each other. There will be differences between them, and there will also be differences between the threshold voltages of NMOS transistors formed on different wafers using the same process, due to the V DD between and V THN101 is proportional to, and the proportionality factor is greater than 1, which will make V DD will be subject to V THN101 effect, and finally make the discreteness of the flipping voltage

Images